US20070159488A1 - Parallel Array Architecture for a Graphics Processor - Google Patents

Parallel Array Architecture for a Graphics Processor Download PDF

Info

Publication number
US20070159488A1
US20070159488A1 US11/611,745 US61174506A US2007159488A1 US 20070159488 A1 US20070159488 A1 US 20070159488A1 US 61174506 A US61174506 A US 61174506A US 2007159488 A1 US2007159488 A1 US 2007159488A1
Authority
US
United States
Prior art keywords
pixel
processing
data
processing clusters
frame buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/611,745
Inventor
John Danskin
John Montrym
John Lindholm
Steven Molnar
Mark French
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corp filed Critical Nvidia Corp
Priority to US11/611,745 priority Critical patent/US20070159488A1/en
Assigned to NVIDIA CORPORATION reassignment NVIDIA CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DANSKIN, JOHN M., FRENCH, MARK, MOLNAR, STEVEN E., LINDHOLM, JOHN ERIK, MONTRYM, JOHN S.
Publication of US20070159488A1 publication Critical patent/US20070159488A1/en
Priority to US13/269,462 priority patent/US8730249B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/005General purpose rendering architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015One dimensional arrays, e.g. rings, linear arrays, buses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363Graphics controllers
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00Indexing scheme for image generation or computer graphics
    • G06T2210/52Parallel processing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/06Use of more than one graphics processor to process data before displaying to one or more screens
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/122Tiling

Definitions

  • the present invention relates in general to graphics processors, and in particular to a parallel array architecture for a graphics processor.
  • Parallel processing techniques enhance throughput of a processor or multiprocessor system when multiple independent computations need to be performed.
  • a computation can be divided into tasks that are defined by programs, with each task being performed as a separate thread.
  • a “thread” refers generally to an instance of execution of a particular program using particular input data
  • a “program” refers to a sequence of executable instructions that produces result data from input data.
  • Parallel threads are executed simultaneously using different processing engines inside the processor.
  • processor architectures support parallel processing.
  • the earliest such architectures used multiple discrete processors networked together.
  • multiple processing cores have been fabricated on a single chip. These cores are controlled in various ways.
  • MIMD multiple-instruction, multiple data
  • SIMD single-instruction, multiple-data
  • a core has a single instruction unit that issues the same instruction in parallel to multiple processing engines, which execute the instruction on different input operands.
  • SIMD machines generally have advantages in chip area (since only one instruction unit is needed) and therefore cost; the downside is that parallelism is only available to the extent that multiple instances of the same instruction can be executed concurrently.
  • SIMD architectures Conventional graphics processors use very wide SIMD architectures to achieve high throughput in image-rendering applications. Such applications generally entail executing the same programs (vertex shaders or pixel shaders) on large numbers of objects (vertices or pixels). Since each object is processed independently of all others but using the same sequence of operations, a SIMD architecture provides considerable performance enhancement at reasonable cost.
  • a GPU includes one SIMD core that executes vertex shader programs, and another SIMD core of comparable size that executes pixel shader programs. In high-end GPUs, multiple sets of SIMD cores are sometimes provided to support an even higher degree of parallelism.
  • the pixel shader core may run at maximum throughput while the vertex core is idle, waiting for already-processed vertices to move into the pixel shader stage of the pipeline.
  • the vertex shader core may run at maximum throughput while the pixel core is idle, waiting for new vertices to be supplied. In either case, some fraction of available processing cycles is effectively wasted.
  • Embodiments of the present invention provide graphics processors that use a scalable multithreaded core array to execute vertex shader programs, geometry shader programs, and/or pixel shader programs in any combination during rendering operations.
  • the core array includes a number of multithreaded processing cores arranged in one or more clusters, with cores in the same cluster being controlled by a shared core interface.
  • the cluster or core in which the program is to be executed is advantageously selected based on the location of the pixel within the image area.
  • the screen is tiled, with each tile being assigned to one or another of the processing clusters (or to a specific core within a processing cluster).
  • the tiles assigned to a given processing cluster or core are advantageously scattered across the screen to provide approximate load balancing.
  • the processing core or cluster includes a raster operations unit that integrates newly generated pixel data with existing data in a frame buffer.
  • the frame buffer can be partitioned to match the number of processing clusters, with each cluster writing all of its data to one partition. In other embodiments, the number of partitions of the frame buffer need not match the number of processing clusters in use.
  • a crossbar or similar circuit structure may provide a configurable coupling between the processing clusters and the frame buffer partitions, so that any processing cluster can be coupled to any frame buffer partitions; in some embodiments, the crossbar is omitted, improving memory locality.
  • FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention
  • FIG. 2 is a block diagram of a rendering pipeline that can be implemented in a graphics processor according to an embodiment of the present invention
  • FIG. 3 is a block diagram of a multithreaded core array for a graphics processor according to an embodiment of the present invention
  • FIG. 4 illustrates one possible tiling of an image area into a number of tiles according to an embodiment of the present invention
  • FIG. 5 is a simplified block diagram illustrating a coupling between processing clusters and a frame buffer according to an embodiment of the present invention.
  • FIG. 6 is a simplified block diagram illustrating a coupling between processing clusters and a frame buffer according to another embodiment of the present invention.
  • FIG. 1 is a block diagram of a computer system 100 according to an embodiment of the present invention.
  • Computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 communicating via a bus path that includes a memory bridge 105 .
  • Memory bridge 105 is connected via a bus path 106 to an I/O (input/output) bridge 107 .
  • I/O bridge 107 receives user input from one or more user input devices 108 (e.g., keyboard, mouse) and forwards the input to CPU 102 via bus 106 and memory bridge 105 .
  • user input devices 108 e.g., keyboard, mouse
  • Visual output is provided on a pixel based display device 110 (e.g., a conventional CRT or LCD based monitor) operating under control of a graphics subsystem 112 coupled to memory bridge 105 via a bus 113 .
  • a system disk 114 is also connected to I/O bridge 107 .
  • a switch 116 provides connections between I/O bridge 107 and other components such as a network adapter 118 and various add-in cards 120 , 121 .
  • Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, and the like, may also be connected to I/O bridge 107 .
  • Bus connections among the various components may be implemented using bus protocols such as PCI (Peripheral Component Interconnect), PCI Express (PCI-E), AGP (Accelerated Graphics Port), HyperTransport, or any other bus protocol(s), and connections between different devices may use different protocols as is known in the art.
  • PCI Peripheral Component Interconnect
  • PCI-E PCI Express
  • AGP Accelerated Graphics Port
  • HyperTransport or any other bus protocol(s)
  • Graphics processing subsystem 112 includes a graphics processing unit (GPU) 122 and a graphics memory 124 , which may be implemented, e.g., using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), and memory devices.
  • GPU 122 may be configured to perform various tasks related to generating pixel data from graphics data supplied by CPU 102 and/or system memory 104 via memory bridge 105 and bus 113 , interacting with graphics memory 124 to store and update pixel data, and the like.
  • GPU 122 may generate pixel data from 2-D or 3-D scene data provided by various programs executing on CPU 102 .
  • GPU 122 may also store pixel data received via memory bridge 105 to graphics memory 124 with or without further processing.
  • GPU 122 also includes a scanout module configured to deliver pixel data from graphics memory 124 to display device 110 .
  • CPU 102 operates as the master processor of system 100 , controlling and coordinating operations of other system components.
  • CPU 102 issues commands that control the operation of GPU 122 .
  • CPU 102 writes a stream of commands for GPU 122 to a command buffer, which may be in system memory 104 , graphics memory 124 , or another storage location accessible to both CPU 102 and GPU 122 .
  • GPU 122 reads the command stream from the command buffer and executes commands asynchronously with operation of CPU 102 .
  • the commands may include conventional rendering commands for generating images as well as general-purpose computation commands that enable applications executing on CPU 102 to leverage the computational power of GPU 122 for data processing that may be unrelated to image generation.
  • system memory 104 is connected to CPU 102 directly rather than through a bridge, and other devices communicate with system memory 104 via memory bridge 105 and CPU 102 .
  • graphics subsystem 112 is connected to I/O bridge 107 rather than to memory bridge 105 .
  • I/O bridge 107 and memory bridge 105 might be integrated into a single chip.
  • switch 116 is eliminated, and network adapter 118 and add-in cards 120 , 121 connect directly to I/O bridge 107 .
  • graphics system 112 is implemented as an add-in card that can be inserted into an expansion slot of system 100 .
  • a GPU is integrated on a single chip with a bus bridge, such as memory bridge 105 or I/O bridge 107 .
  • a GPU may be provided with any amount of local graphics memory, including no local memory, and may use local memory and system memory in any combination. For instance, in a unified memory architecture (UMA) embodiment, no dedicated graphics memory device is provided, and the GPU uses system memory exclusively or almost exclusively.
  • UMA unified memory architecture
  • the GPU may be integrated into a bus bridge chip or provided as a discrete chip with a high-speed bus (e.g., PCI-E) connecting the GPU to the bridge chip and system memory.
  • PCI-E high-speed bus
  • any number of GPUs may be included in a system, e.g., by including multiple GPUs on a single graphics card or by connecting multiple graphics cards to bus 113 . Multiple GPUs may be operated in parallel to generate images for the same display device or for different display devices.
  • GPUs embodying aspects of the present invention may be incorporated into a variety of devices, including general purpose computer systems, video game consoles and other special purpose computer systems, DVD players, handheld devices such as mobile phones or personal digital assistants, and so on.
  • FIG. 2 is a block diagram of a rendering pipeline 200 that can be implemented in GPU 122 of FIG. 1 according to an embodiment of the present invention.
  • rendering pipeline 200 is implemented using an architecture in which any applicable vertex shader programs, geometry shader programs, and pixel shader programs are executed using the same parallel-processing hardware, referred to herein as a “multithreaded core array” 202 .
  • Multithreaded core array 202 is described further below.
  • rendering pipeline 200 includes a front end 204 and data assembler 206 , a setup module 208 , a rasterizer 210 , a color assembly module 212 , and a raster operations module (ROP) 214 , each of which can be implemented using conventional integrated circuit technologies or other technologies.
  • setup module 208 a setup module 208 , a rasterizer 210 , a color assembly module 212 , and a raster operations module (ROP) 214 , each of which can be implemented using conventional integrated circuit technologies or other technologies.
  • ROI raster operations module
  • Front end 204 receives state information (STATE), rendering commands (CMD), and geometry data (GDATA), e.g., from CPU 102 of FIG. 1 .
  • CPU 102 provides references to locations in system memory 104 at which geometry data is stored; data assembler 206 retrieves the data from system memory 104 .
  • the state information, rendering commands, and geometry data may be of a generally conventional nature and may be used to define the desired rendered image or images, including geometry, lighting, shading, texture, motion, and/or camera parameters for a scene.
  • the geometry data includes a number of object definitions for objects (e.g., a table, a chair, a person or animal) that may be present in the scene.
  • objects e.g., a table, a chair, a person or animal
  • Objects are advantageously modeled as groups of primitives (e.g., points, lines, triangles and/or other polygons) that are defined by reference to their vertices.
  • a position is specified in an object coordinate system, representing the position of the vertex relative to the object being modeled.
  • each vertex may have various other attributes associated with it.
  • attributes of a vertex may include any property that is specified on a per-vertex basis; for instance, in some embodiments, the vertex attributes include scalar or vector attributes used to determine qualities such as the color, texture, transparency, lighting, shading, and animation of the vertex and its associated geometric primitives.
  • Primitives are generally defined by reference to their vertices, and a single vertex can be included in any number of primitives.
  • each vertex is assigned an index (which may be any unique identifier), and a primitive is defined by providing an ordered list of indices for the vertices making up that primitive.
  • index which may be any unique identifier
  • Other techniques for defining primitives including conventional techniques such as triangle strips or fans may also be used.
  • the state information and rendering commands define processing parameters and actions for various stages of rendering pipeline 200 .
  • Front end 204 directs the state information and rendering commands via a control path (not explicitly shown) to other components of rendering pipeline 200 .
  • these components may respond to received state information by storing or updating values in various control registers that are accessed during processing and may respond to rendering commands by processing data received in the pipeline.
  • Front end 204 directs the geometry data to data assembler 206 .
  • Data assembler 206 formats the geometry data and prepares it for delivery to a geometry module 218 in multithreaded core array 202 .
  • Geometry module 218 directs programmable processing engines (not explicitly shown) in multithreaded core array 202 to execute vertex and/or geometry shader programs on the vertex data, with the programs being selected in response to the state information provided by front end 204 .
  • the vertex and/or geometry shader programs can be specified by the rendering application as is known in the art, and different shader programs can be applied to different vertices and/or primitives.
  • the shader program(s) to be used can be stored in system memory or graphics memory and identified to multithreaded core array 202 via suitable rendering commands and state information as is known in the art.
  • vertex shader and/or geometry shader programs can be executed in multiple passes, with different processing operations being performed during each pass.
  • Each vertex and/or geometry shader program determines the number of passes and the operations to be performed during each pass.
  • Vertex and/or geometry shader programs can implement algorithms using a wide range of mathematical and logical operations on vertices and other data, and the programs can include conditional or branching execution paths and direct and indirect memory accesses.
  • Vertex shader programs and geometry shader programs can be used to implement a variety of visual effects, including lighting and shading effects.
  • a vertex program transforms a vertex from its 3D object coordinate system to a 3D clip space or world space coordinate system. This transformation defines the relative positions of different objects in the scene.
  • the transformation can be programmed by including, in the rendering commands and/or data defining each object, a transformation matrix for converting from the object coordinate system of that object to clip space coordinates.
  • the vertex shader program applies this transformation matrix to each vertex of the primitives making up an object.
  • More complex vertex shader programs can be used to implement a variety of visual effects, including lighting and shading, procedural geometry, and animation operations. Numerous examples of such per-vertex operations are known in the art, and a detailed description is omitted as not being critical to understanding the present invention.
  • Geometry shader programs differ from vertex shader programs in that geometry shader programs operate on primitives (groups of vertices) rather than individual vertices.
  • a geometry program may create new vertices and/or remove vertices or primitives from the set of objects being processed.
  • passes through a vertex shader program and a geometry shader program can be alternated to process the geometry data.
  • vertex shader programs and geometry shader programs are executed using the same programmable processing engines in multithreaded core array 202 .
  • a given processing engine may operate as a vertex shader, receiving and executing vertex program instructions, and at other times the same processing engine may operate as a geometry shader, receiving and executing geometry program instructions.
  • the processing engines can be multithreaded, and different threads executing different types of shader programs may be in flight concurrently in multithreaded core array 202 .
  • geometry module 218 passes the processed geometry data (GDATA′) to setup module 208 .
  • Setup module 208 which may be of generally conventional design, generates edge equations from the clip space or screen space coordinates of each primitive; the edge equations are advantageously usable to determine whether a point in screen space is inside or outside the primitive.
  • Rasterizer 210 which may be of generally conventional design, determines which (if any) pixels are covered by the primitive, e.g., using conventional scan-conversion algorithms.
  • a “pixel” refers generally to a region in 2-D screen space for which a single color value is to be determined; the number and arrangement of pixels can be a configurable parameter of rendering pipeline 200 and might or might not be correlated with the screen resolution of a particular display device.
  • pixel color may be sampled at multiple locations within the pixel (e.g., using conventional supersampling or multisampling techniques), and in some embodiments, supersampling or multisampling is handled within the pixel shader.
  • rasterizer 210 After determining which pixels are covered by a primitive, rasterizer 210 provides the primitive (PRIM), along with a list of screen coordinates (X,Y) of the pixels covered by the primitive, to a color assembly module 212 .
  • Color assembly module 212 associates the primitives and coverage information received from rasterizer 210 with attributes (e.g., color components, texture coordinates, surface normals) of the vertices of the primitive and generates plane equations (or other suitable equations) defining some or all of the attributes as a function of position in screen coordinate space.
  • attributes e.g., color components, texture coordinates, surface normals
  • Color assembly module 212 provides the attribute equations (EQS, which may include e.g., the plane-equation coefficients A, B and C for each primitive that covers at least one pixel and a list of screen coordinates (X,Y) of the covered pixels to a pixel module 224 in multithreaded core array 202 .
  • Pixel module 224 directs programmable processing engines (not explicitly shown) in multithreaded core array 202 to execute one or more pixel shader programs on each pixel covered by the primitive, with the program(s) being selected in response to the state information provided by front end 204 .
  • rendering applications can specify the pixel shader program to be used for any given set of pixels.
  • Pixel shader programs can be used to implement a variety of visual effects, including lighting and shading effects, reflections, texture blending, procedural texture generation, and so on. Numerous examples of such per-pixel operations are known in the art and a detailed description is omitted as not being critical to understanding the present invention. Pixel shader programs can implement algorithms using a wide range of mathematical and logical operations on pixels and other data, and the programs can include conditional or branching execution paths and direct and indirect memory accesses.
  • Pixel shader programs are advantageously executed in multithreaded core array 202 using the same programmable processing engines that also execute the vertex and/or geometry shader programs.
  • a given processing engine may operate as a vertex shader, receiving and executing vertex program instructions; at other times the same processing engine may operates as a geometry shader, receiving and executing geometry program instructions; and at still other times the same processing engine may operate as a pixel shader, receiving and executing pixel shader program instructions.
  • the multithreaded core array can provide natural load-balancing between pixel and vertex processing: where the application is geometry intensive (e.g., many small primitives), a larger fraction of the processing cycles in multithreaded core array 202 will tend to be devoted to vertex and/or geometry shaders, and where the application is pixel intensive (e.g., fewer and larger primitives shaded using complex pixel shader programs with multiple textures and the like), a larger fraction of the processing cycles will tend to be devoted to pixel shaders.
  • geometry intensive e.g., many small primitives
  • pixel intensive e.g., fewer and larger primitives shaded using complex pixel shader programs with multiple textures and the like
  • pixel module 224 provides the processed pixels (PDATA) to ROP 214 .
  • ROP 214 which may be of generally conventional design, integrates the pixel values received from pixel module 224 with pixels of the image under construction in frame buffer 226 , which may be located, e.g., in graphics memory 124 .
  • ROP 214 can mask pixels or blend new pixels with pixels previously written to the rendered image. Depth buffers, alpha buffers, and stencil buffers can also be used to determine the contribution (if any) of each incoming pixel to the rendered image.
  • Pixel data PDATA′ corresponding to the appropriate combination of each incoming pixel value and any previously stored pixel value is written back to frame buffer 226 .
  • frame buffer 226 can be scanned out to a display device and/or subjected to further processing.
  • rasterization may be performed in stages, with a “coarse” rasterizer that processes the entire screen in blocks (e.g., 16 ⁇ 16 pixels) to determine which, if any, blocks the triangle covers (or partially covers), followed by a “fine” rasterizer that processes the individual pixels within any block that is determined to be at least partially covered.
  • the fine rasterizer is contained within pixel module 224 .
  • some operations conventionally performed by a ROP may be performed within pixel module 224 before the pixel data is forwarded to ROP 214 .
  • multithreaded core array 202 includes two or more geometry modules 218 and an equal number of pixel modules 224 that operate in parallel. Each geometry module and pixel module jointly controls a different subset of the processing engines in multithreaded core array 202 .
  • multithreaded core array 202 provides a highly parallel architecture that supports concurrent execution of a large number of instances of vertex, geometry, and/or pixel shader programs in various combinations.
  • FIG. 3 is a block diagram of multithreaded core array 202 according to an embodiment of the present invention.
  • multithreaded core array 202 includes some number (N) of processing clusters 302 .
  • N some number of processing clusters 302 .
  • N any number (e.g., 1, 4, 8, or any other number) of processing clusters may be provided.
  • N e.g. 1, 4, 8, or any other number
  • FIG. 3 one processing cluster 302 is shown in detail; it is to be understood that other processing clusters 302 can be of similar or identical design.
  • Each processing cluster 302 includes a geometry controller 304 (implementing geometry module 218 of FIG. 2 ) and a pixel controller 306 (implementing pixel module 224 of FIG. 2 ). Geometry controller 304 and pixel controller 306 each communicate with a core interface 308 .
  • Core interface 308 controls a number (A) of cores 310 that include the processing engines of multithreaded core array 202 . Any number M (e.g., 1, 2, 4 or any other number) of cores 310 may be connected to a single core interface.
  • Each core 310 is advantageously implemented as a multithreaded execution core capable of supporting a large number (e.g., 100 or more) of concurrent execution threads (where the term “thread” refers to an instance of a particular program executing on a particular set of input data), including a combination of vertex threads, geometry threads, and pixel threads.
  • each core 310 implements a P-way SIMD architecture to execute P threads in parallel, where P is an arbitrary integer (e.g., 8, 16, 32) and is capable of managing a number G (e.g. 18, 24, etc.) of groups of P threads concurrently.
  • P is an arbitrary integer (e.g., 8, 16, 32) and is capable of managing a number G (e.g. 18, 24, etc.) of groups of P threads concurrently.
  • G e.g. 18, 24, etc.
  • Core interface 308 also controls a texture pipeline 314 that is shared among cores 310 .
  • Texture pipeline 314 which may be of generally conventional design, advantageously includes logic circuits configured to receive texture coordinates, to fetch texture data corresponding to the texture coordinates from memory, and to filter the texture data according to various algorithms. Conventional filtering algorithms including bilinear and trilinear filtering may be used.
  • a core 310 encounters a texture instruction in one of its threads, it provides the texture coordinates to texture pipeline 314 via core interface 308 .
  • Texture pipeline 314 processes the texture instruction and returns the result to the core 310 via core interface 308 . Texture processing by pipeline 314 may consume a significant number of clock cycles, and while a thread is waiting for the texture result, core 310 advantageously continues to execute other threads.
  • data assembler 206 ( FIG. 2 ) provides geometry data GDATA to processing clusters 302 .
  • data assembler 206 divides the incoming stream of geometry data into portions and selects, e.g., based on availability of execution resources, which of processing clusters 302 is to receive the next portion of the geometry data. That portion is delivered to geometry controller 304 in the selected processing cluster 302 .
  • Geometry controller 304 forwards the received data to core interface 308 , which loads the vertex data into a core 310 , then instructs core 310 to launch the appropriate vertex shader program.
  • core interface 308 signals geometry controller 304 . If a geometry shader program is to be executed, geometry controller 304 instructs core interface 308 to launch the geometry shader program.
  • the processed vertex data is returned to geometry controller 304 upon completion of the vertex shader program, and geometry controller 304 instructs core interface 308 to reload the data before executing the geometry shader program.
  • geometry controller 304 provides the processed geometry data (GDATA′) to setup module 208 of FIG. 2 .
  • color assembly module 212 ( FIG. 2 ) provides attribute equations EQS for a primitive and pixel coordinates (X,Y) of pixels covered by the primitive to processing clusters 302 .
  • color assembly module 212 divides the incoming stream of coverage data into portions and selects, e.g., based on availability of execution resources or the location of the primitive in screen coordinates, which of processing clusters 302 is to receive the next portion of the data. That portion is delivered to pixel controller 306 in the selected processing cluster 302 .
  • Pixel controller 306 delivers the data to core interface 308 , which loads the pixel data into a core 310 , then instructs the core 310 to launch the pixel shader program. Where core 310 is multithreaded, pixel shader programs, geometry shader programs, and vertex shader programs can all be executed concurrently in the same core 310 . Upon completion of the pixel shader program, core interface 308 delivers the processed pixel data to pixel controller 306 , which forwards the pixel data PDATA to ROP unit 214 ( FIG. 2 ).
  • multithreaded core array described herein is illustrative and that variations and modifications are possible. Any number of processing clusters may be provided, and each processing cluster may include any number of cores. In some embodiments, shaders of certain types may be restricted to executing in certain processing clusters or in certain cores; for instance, geometry shaders might be restricted to executing in core 310 ( 0 ) of each processing cluster. Such design choices may be driven by considerations of hardware size and complexity versus performance, as is known in the art.
  • a shared texture pipeline is also optional; in some embodiments, each core might have its own texture pipeline or might leverage general-purpose functional units to perform texture computations.
  • Data to be processed can be distributed to the processing clusters in various ways.
  • the data assembler or other source of geometry data
  • color assembly module or other source of pixel-shader input data
  • input data is forwarded from one processing cluster to the next until a processing cluster with capacity to process the data accepts it.
  • processing clusters are selected based on properties of the input data, such as the screen coordinates of pixels to be processed.
  • the multithreaded core array can also be leveraged to perform general-purpose computations that might or might not be related to rendering images.
  • any computation that can be expressed in a data-parallel decomposition can be handled by the multithreaded core array as an array of threads executing in a single core. Results of such computations can be written to the frame buffer and read back into system memory.
  • pixels to be processed by a pixel shader program are directed to a processing cluster 302 ( FIG. 3 ) based on the position of the pixels within the image area.
  • the image area can be divided into a number of tiles.
  • Each tile is associated with one of the processing clusters 302 in such a way that the tiles associated with one cluster are scattered across the image area (i.e., at least some of the tiles associated with one processing cluster are not contiguous with one another).
  • FIG. 4 illustrates one possible tiling of an image area 400 into a large number of tiles 402 according to an embodiment of the present invention.
  • Each tile 402 might be, e.g., 16 ⁇ 16 pixels or any other convenient size.
  • multithreaded core array 202 of FIG. 3 includes eight processing clusters 302 ( 0 ) through 302 ( 7 ).
  • Each tile 402 in FIG. 4 contains a number i (0 through 7) indicating which processing core 302 ( i ) processes pixels in that tile.
  • each processing cluster 302 is assigned an equal (or nearly equal) number of tiles 402 within image area 400 , and the tiles assigned to each cluster 302 are not contiguous with each other.
  • Suitable pixel distribution logic can be included in rendering pipeline 200 , e.g., in color assembly module 212 of FIG. 2 .
  • the tiles may be of any size.
  • the size and number of tiles is configurable, with tile size being chosen based on application characteristics such as whether a multisampling mode is in use.
  • the arrangement of tiles assigned to each processing cluster can vary as desired.
  • Tiles may be assigned to any number of processing clusters, up to the total number that are present in a particular GPU. In some embodiments, tiles are assigned to fewer than all of the processing clusters.
  • a GPU can render images using only some of its processing clusters to process pixel threads. As long as at least one processing cluster is available, the GPU will be able to render images, albeit at reduced throughput.
  • Running with some clusters disabled from processing pixel threads may be useful, e.g., for operating in a reduced-power mode (some cores or clusters can be powered down while others operate), for determining minimum performance requirements (without requiring the availability of different GPUs), and/or for providing tolerance against defects in one or another of the cores.
  • tiles are assigned to particular cores 310 rather than to processing clusters 302 .
  • each pixel controller 306 in FIG. 3 includes its own ROP that communicates pixels to frame buffer 226 of FIG. 2 .
  • a coupling from processing clusters 302 to the frame buffer is provided.
  • frame buffer 226 is partitioned into N partitions.
  • Each cluster 302 is coupled to a different one of the N partitions.
  • FIG. 5 is a simplified block diagram illustrating a coupling between processing clusters 302 and a frame buffer 500 according to an embodiment of the present invention.
  • frame buffer 226 of FIG. 2 might include multiple frame buffers 500 , where each frame buffer 500 stores a specified quantity on a per-pixel basis for the same image.
  • frame buffer 226 includes a Z buffer; color component buffers (e.g., for red, green and blue color components); and a transparency (alpha) buffer.
  • pixel as used herein refers to sampling locations within the image, which might or might not correspond to the number of active pixels in a given display device. For simplicity, only one frame buffer 500 is shown; it is to be understood that the same partitioning can be applied to each frame buffer for an image.
  • Frame buffer 500 is partitioned (physically or logically) into N partitions 502 , with each partition being large enough to store the data for at least 1/N of the pixels in the image.
  • Each of the N processing clusters 302 is coupled to one of the N partitions 502 .
  • processing cluster 302 ( 0 ) stores all of its output pixel data in partition 502 ( 0 ), processing cluster 302 ( 1 ) in partition 502 ( 1 ) and so on.
  • the display (scanout) logic advantageously observes the correct display ordering of the data when accessing frame buffer 500 ; in particular, it is not required that partitions be read out sequentially.
  • processing cores 302 might be used to generate pixels.
  • only processing cluster 302 ( 0 ) provides pixels to frame buffer partition 502 ( 0 ). Accordingly, if processing cluster 302 ( 0 ) is not operated to generate pixels, frame buffer partition 502 ( 0 ) will not be used.
  • the image area can be retiled or tiles can be reassigned among processing clusters 302 ( 1 ) through 302 (N ⁇ 1) such that the area is divided among N ⁇ 1 processing clusters.
  • the sampling resolution might need to be reduced, e.g., if frame buffer partitions 502 ( 1 ) through 502 (N ⁇ 1) do not provide enough space to store all of the pixel data for the image at the original sampling resolution.
  • frame buffer 500 can be repartitioned to match the number of processing clusters 302 available.
  • each processing cluster can access multiple frame buffer partitions.
  • FIG. 6 is a simplified block diagram illustrating a coupling between processing clusters 302 and a frame buffer 600 according to an embodiment of the present invention. It is to be understood that frame buffer 226 of FIG. 2 might include multiple frame buffers 600 , where each frame buffer 600 stores a specified quantity on a per-pixel basis for the same image as described above with reference to frame buffer 500 . It is to be understood that any number of frame buffers 600 may be provided. For simplicity, only one frame buffer 600 is shown; it is to be understood that the partitioning can be applied to each frame buffer for an image.
  • Frame buffer 600 is partitioned (physically or logically) into a number B of partitions 602 , where B might be equal to or different from the number N of processing clusters 302 .
  • Processing clusters 302 are coupled to partitions 602 via a crossbar 604 .
  • Each cluster 302 can write pixel data to any one (or more) of the B partitions 602 .
  • crossbar 604 is configurable, allowing the coupling of processing clusters 302 to frame buffer partitions 602 to be modified as desired. For example, as noted above, in some embodiments, fewer than all of processing cores 302 might be used to generate pixels. In the embodiment shown in FIG. 6 , if processing core 302 ( 0 ) is disabled, crossbar 604 can be reconfigured so that all frame buffer partitions 602 are still accessible to one or another of processing cores 302 .
  • the display (scanout) logic is advantageously configurable such that the frame buffer data is correctly scanned out regardless of the configuration of crossbar 604 or the assignment of tiles to processing cores 302 .
  • each frame buffer may be partitioned into B partitions in the manner described.
  • the number of partitions is not the same for all frame buffers; for instance, a Z buffer might have more or fewer partitions than a color buffer.

Abstract

A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. The pixel distribution logic selects one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area. The processing clusters can be mapped directly to the frame buffers partitions without a crossbar so that pixel data is delivered directly from the processing cluster to the appropriate frame buffer partitions. Alternatively, a crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions. The crossbar is configured such that pixel data generated by any one of the processing clusters is deliverable to any one of the frame buffer partitions.

Description

    CROSS-REFERENCES TO RELATED APPLICATIONS
  • The present application claims the benefit of U.S. Provisional Application No. 60/752,265, filed Dec. 19, 2005, which is incorporated herein by reference in its entirety for all purposes.
  • The present application is related to the following commonly-assigned co-pending U.S. patent applications: application Ser. No. 11/290,303, filed Nov. 29, 2005; application Ser. No. 11/289,828, filed Nov. 29, 2005; and application Ser. No. 11/311,993, filed Dec. 19, 2005, which are incorporated in their entirety, herein, by reference for all purposes.
  • BACKGROUND OF THE INVENTION
  • The present invention relates in general to graphics processors, and in particular to a parallel array architecture for a graphics processor.
  • Parallel processing techniques enhance throughput of a processor or multiprocessor system when multiple independent computations need to be performed. A computation can be divided into tasks that are defined by programs, with each task being performed as a separate thread. (As used herein, a “thread” refers generally to an instance of execution of a particular program using particular input data, and a “program” refers to a sequence of executable instructions that produces result data from input data.) Parallel threads are executed simultaneously using different processing engines inside the processor.
  • Numerous existing processor architectures support parallel processing. The earliest such architectures used multiple discrete processors networked together. More recently, multiple processing cores have been fabricated on a single chip. These cores are controlled in various ways. In some instances, known as multiple-instruction, multiple data (MIMD) machines, each core independently fetches and issues its own instructions to its own processing engine (or engines). In other instances, known as single-instruction, multiple-data (SIMD) machines, a core has a single instruction unit that issues the same instruction in parallel to multiple processing engines, which execute the instruction on different input operands. SIMD machines generally have advantages in chip area (since only one instruction unit is needed) and therefore cost; the downside is that parallelism is only available to the extent that multiple instances of the same instruction can be executed concurrently.
  • Conventional graphics processors use very wide SIMD architectures to achieve high throughput in image-rendering applications. Such applications generally entail executing the same programs (vertex shaders or pixel shaders) on large numbers of objects (vertices or pixels). Since each object is processed independently of all others but using the same sequence of operations, a SIMD architecture provides considerable performance enhancement at reasonable cost. Typically, a GPU includes one SIMD core that executes vertex shader programs, and another SIMD core of comparable size that executes pixel shader programs. In high-end GPUs, multiple sets of SIMD cores are sometimes provided to support an even higher degree of parallelism.
  • These designs have several shortcomings. First, the separate processing cores for vertex and shader programs are separately designed and tested, often leading to at least some duplication of effort. Second, the division of the graphics processing load between vertex operations and pixel operations varies greatly from one application to another. As is known in the art, detail can be added to an image by using many small primitives, which increases the load on the vertex shader core, and/or by using complex texture-mapping and pixel shading operations, which increases the load on the pixel shader core. In most cases, the loads are not perfectly balanced, and one core or the other is underused. For instance, in a pixel-intensive application, the pixel shader core may run at maximum throughput while the vertex core is idle, waiting for already-processed vertices to move into the pixel shader stage of the pipeline. Conversely, in a vertex-intensive application, the vertex shader core may run at maximum throughput while the pixel core is idle, waiting for new vertices to be supplied. In either case, some fraction of available processing cycles is effectively wasted.
  • It would therefore be desirable to provide a graphics processor that can adapt to varying loads on different shaders while maintaining a high degree of parallelism.
  • BRIEF SUMMARY OF THE INVENTION
  • Embodiments of the present invention provide graphics processors that use a scalable multithreaded core array to execute vertex shader programs, geometry shader programs, and/or pixel shader programs in any combination during rendering operations. The core array includes a number of multithreaded processing cores arranged in one or more clusters, with cores in the same cluster being controlled by a shared core interface.
  • In embodiments where a pixel shader program is to be executed, the cluster or core in which the program is to be executed is advantageously selected based on the location of the pixel within the image area. In one embodiment, the screen is tiled, with each tile being assigned to one or another of the processing clusters (or to a specific core within a processing cluster). The tiles assigned to a given processing cluster or core are advantageously scattered across the screen to provide approximate load balancing.
  • In some embodiments, the processing core or cluster includes a raster operations unit that integrates newly generated pixel data with existing data in a frame buffer. The frame buffer can be partitioned to match the number of processing clusters, with each cluster writing all of its data to one partition. In other embodiments, the number of partitions of the frame buffer need not match the number of processing clusters in use. A crossbar or similar circuit structure may provide a configurable coupling between the processing clusters and the frame buffer partitions, so that any processing cluster can be coupled to any frame buffer partitions; in some embodiments, the crossbar is omitted, improving memory locality.
  • The following detailed description together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention;
  • FIG. 2 is a block diagram of a rendering pipeline that can be implemented in a graphics processor according to an embodiment of the present invention;
  • FIG. 3 is a block diagram of a multithreaded core array for a graphics processor according to an embodiment of the present invention;
  • FIG. 4 illustrates one possible tiling of an image area into a number of tiles according to an embodiment of the present invention;
  • FIG. 5 is a simplified block diagram illustrating a coupling between processing clusters and a frame buffer according to an embodiment of the present invention; and
  • FIG. 6 is a simplified block diagram illustrating a coupling between processing clusters and a frame buffer according to another embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • System Overview
  • FIG. 1 is a block diagram of a computer system 100 according to an embodiment of the present invention. Computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 communicating via a bus path that includes a memory bridge 105. Memory bridge 105 is connected via a bus path 106 to an I/O (input/output) bridge 107. I/O bridge 107 receives user input from one or more user input devices 108 (e.g., keyboard, mouse) and forwards the input to CPU 102 via bus 106 and memory bridge 105. Visual output is provided on a pixel based display device 110 (e.g., a conventional CRT or LCD based monitor) operating under control of a graphics subsystem 112 coupled to memory bridge 105 via a bus 113. A system disk 114 is also connected to I/O bridge 107. A switch 116 provides connections between I/O bridge 107 and other components such as a network adapter 118 and various add-in cards 120, 121. Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, and the like, may also be connected to I/O bridge 107. Bus connections among the various components may be implemented using bus protocols such as PCI (Peripheral Component Interconnect), PCI Express (PCI-E), AGP (Accelerated Graphics Port), HyperTransport, or any other bus protocol(s), and connections between different devices may use different protocols as is known in the art.
  • Graphics processing subsystem 112 includes a graphics processing unit (GPU) 122 and a graphics memory 124, which may be implemented, e.g., using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), and memory devices. GPU 122 may be configured to perform various tasks related to generating pixel data from graphics data supplied by CPU 102 and/or system memory 104 via memory bridge 105 and bus 113, interacting with graphics memory 124 to store and update pixel data, and the like. For example, GPU 122 may generate pixel data from 2-D or 3-D scene data provided by various programs executing on CPU 102. GPU 122 may also store pixel data received via memory bridge 105 to graphics memory 124 with or without further processing. GPU 122 also includes a scanout module configured to deliver pixel data from graphics memory 124 to display device 110.
  • CPU 102 operates as the master processor of system 100, controlling and coordinating operations of other system components. In particular, CPU 102 issues commands that control the operation of GPU 122. In some embodiments, CPU 102 writes a stream of commands for GPU 122 to a command buffer, which may be in system memory 104, graphics memory 124, or another storage location accessible to both CPU 102 and GPU 122. GPU 122 reads the command stream from the command buffer and executes commands asynchronously with operation of CPU 102. The commands may include conventional rendering commands for generating images as well as general-purpose computation commands that enable applications executing on CPU 102 to leverage the computational power of GPU 122 for data processing that may be unrelated to image generation.
  • It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The bus topology, including the number and arrangement of bridges, may be modified as desired. For instance, in some embodiments, system memory 104 is connected to CPU 102 directly rather than through a bridge, and other devices communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, graphics subsystem 112 is connected to I/O bridge 107 rather than to memory bridge 105. In still other embodiments, I/O bridge 107 and memory bridge 105 might be integrated into a single chip. The particular components shown herein are optional; for instance, any number of add-in cards or peripheral devices might be supported. In some embodiments, switch 116 is eliminated, and network adapter 118 and add-in cards 120, 121 connect directly to I/O bridge 107.
  • The connection of GPU 122 to the rest of system 100 may also be varied. In some embodiments, graphics system 112 is implemented as an add-in card that can be inserted into an expansion slot of system 100. In other embodiments, a GPU is integrated on a single chip with a bus bridge, such as memory bridge 105 or I/O bridge 107.
  • A GPU may be provided with any amount of local graphics memory, including no local memory, and may use local memory and system memory in any combination. For instance, in a unified memory architecture (UMA) embodiment, no dedicated graphics memory device is provided, and the GPU uses system memory exclusively or almost exclusively. In UMA embodiments, the GPU may be integrated into a bus bridge chip or provided as a discrete chip with a high-speed bus (e.g., PCI-E) connecting the GPU to the bridge chip and system memory.
  • It is also to be understood that any number of GPUs may be included in a system, e.g., by including multiple GPUs on a single graphics card or by connecting multiple graphics cards to bus 113. Multiple GPUs may be operated in parallel to generate images for the same display device or for different display devices.
  • In addition, GPUs embodying aspects of the present invention may be incorporated into a variety of devices, including general purpose computer systems, video game consoles and other special purpose computer systems, DVD players, handheld devices such as mobile phones or personal digital assistants, and so on.
  • Rendering Pipeline Overview
  • FIG. 2 is a block diagram of a rendering pipeline 200 that can be implemented in GPU 122 of FIG. 1 according to an embodiment of the present invention. In this embodiment, rendering pipeline 200 is implemented using an architecture in which any applicable vertex shader programs, geometry shader programs, and pixel shader programs are executed using the same parallel-processing hardware, referred to herein as a “multithreaded core array” 202. Multithreaded core array 202 is described further below.
  • In addition to multithreaded core array 202, rendering pipeline 200 includes a front end 204 and data assembler 206, a setup module 208, a rasterizer 210, a color assembly module 212, and a raster operations module (ROP) 214, each of which can be implemented using conventional integrated circuit technologies or other technologies.
  • Front end 204 receives state information (STATE), rendering commands (CMD), and geometry data (GDATA), e.g., from CPU 102 of FIG. 1. In some embodiments, rather than providing geometry data directly, CPU 102 provides references to locations in system memory 104 at which geometry data is stored; data assembler 206 retrieves the data from system memory 104. The state information, rendering commands, and geometry data may be of a generally conventional nature and may be used to define the desired rendered image or images, including geometry, lighting, shading, texture, motion, and/or camera parameters for a scene.
  • In one embodiment, the geometry data includes a number of object definitions for objects (e.g., a table, a chair, a person or animal) that may be present in the scene. Objects are advantageously modeled as groups of primitives (e.g., points, lines, triangles and/or other polygons) that are defined by reference to their vertices. For each vertex, a position is specified in an object coordinate system, representing the position of the vertex relative to the object being modeled. In addition to a position, each vertex may have various other attributes associated with it. In general, attributes of a vertex may include any property that is specified on a per-vertex basis; for instance, in some embodiments, the vertex attributes include scalar or vector attributes used to determine qualities such as the color, texture, transparency, lighting, shading, and animation of the vertex and its associated geometric primitives.
  • Primitives, as already noted, are generally defined by reference to their vertices, and a single vertex can be included in any number of primitives. In some embodiments, each vertex is assigned an index (which may be any unique identifier), and a primitive is defined by providing an ordered list of indices for the vertices making up that primitive. Other techniques for defining primitives (including conventional techniques such as triangle strips or fans) may also be used.
  • The state information and rendering commands define processing parameters and actions for various stages of rendering pipeline 200. Front end 204 directs the state information and rendering commands via a control path (not explicitly shown) to other components of rendering pipeline 200. As is known in the art, these components may respond to received state information by storing or updating values in various control registers that are accessed during processing and may respond to rendering commands by processing data received in the pipeline.
  • Front end 204 directs the geometry data to data assembler 206. Data assembler 206 formats the geometry data and prepares it for delivery to a geometry module 218 in multithreaded core array 202.
  • Geometry module 218 directs programmable processing engines (not explicitly shown) in multithreaded core array 202 to execute vertex and/or geometry shader programs on the vertex data, with the programs being selected in response to the state information provided by front end 204. The vertex and/or geometry shader programs can be specified by the rendering application as is known in the art, and different shader programs can be applied to different vertices and/or primitives. The shader program(s) to be used can be stored in system memory or graphics memory and identified to multithreaded core array 202 via suitable rendering commands and state information as is known in the art. In some embodiments, vertex shader and/or geometry shader programs can be executed in multiple passes, with different processing operations being performed during each pass. Each vertex and/or geometry shader program determines the number of passes and the operations to be performed during each pass. Vertex and/or geometry shader programs can implement algorithms using a wide range of mathematical and logical operations on vertices and other data, and the programs can include conditional or branching execution paths and direct and indirect memory accesses.
  • Vertex shader programs and geometry shader programs can be used to implement a variety of visual effects, including lighting and shading effects. For instance, in a simple embodiment, a vertex program transforms a vertex from its 3D object coordinate system to a 3D clip space or world space coordinate system. This transformation defines the relative positions of different objects in the scene. In one embodiment, the transformation can be programmed by including, in the rendering commands and/or data defining each object, a transformation matrix for converting from the object coordinate system of that object to clip space coordinates. The vertex shader program applies this transformation matrix to each vertex of the primitives making up an object. More complex vertex shader programs can be used to implement a variety of visual effects, including lighting and shading, procedural geometry, and animation operations. Numerous examples of such per-vertex operations are known in the art, and a detailed description is omitted as not being critical to understanding the present invention.
  • Geometry shader programs differ from vertex shader programs in that geometry shader programs operate on primitives (groups of vertices) rather than individual vertices. Thus, in some instances, a geometry program may create new vertices and/or remove vertices or primitives from the set of objects being processed. In some embodiments, passes through a vertex shader program and a geometry shader program can be alternated to process the geometry data.
  • In some embodiments, vertex shader programs and geometry shader programs are executed using the same programmable processing engines in multithreaded core array 202. Thus, at certain times, a given processing engine may operate as a vertex shader, receiving and executing vertex program instructions, and at other times the same processing engine may operate as a geometry shader, receiving and executing geometry program instructions. The processing engines can be multithreaded, and different threads executing different types of shader programs may be in flight concurrently in multithreaded core array 202.
  • After the vertex and/or geometry shader programs have executed, geometry module 218 passes the processed geometry data (GDATA′) to setup module 208. Setup module 208, which may be of generally conventional design, generates edge equations from the clip space or screen space coordinates of each primitive; the edge equations are advantageously usable to determine whether a point in screen space is inside or outside the primitive.
  • Setup module 208 provides each primitive (PRIM) to rasterizer 210. Rasterizer 210, which may be of generally conventional design, determines which (if any) pixels are covered by the primitive, e.g., using conventional scan-conversion algorithms. As used herein, a “pixel” (or “fragment”) refers generally to a region in 2-D screen space for which a single color value is to be determined; the number and arrangement of pixels can be a configurable parameter of rendering pipeline 200 and might or might not be correlated with the screen resolution of a particular display device. As is known in the art, pixel color may be sampled at multiple locations within the pixel (e.g., using conventional supersampling or multisampling techniques), and in some embodiments, supersampling or multisampling is handled within the pixel shader.
  • After determining which pixels are covered by a primitive, rasterizer 210 provides the primitive (PRIM), along with a list of screen coordinates (X,Y) of the pixels covered by the primitive, to a color assembly module 212. Color assembly module 212 associates the primitives and coverage information received from rasterizer 210 with attributes (e.g., color components, texture coordinates, surface normals) of the vertices of the primitive and generates plane equations (or other suitable equations) defining some or all of the attributes as a function of position in screen coordinate space.
  • These attribute equations are advantageously usable in a pixel shader program to interpolate a value for the attribute at any location within the primitive; conventional techniques can be used to generate the equations. For instance, in one embodiment, color assembly module 212 generates coefficients A, B, and C for a plane equation of the form U=Ax+By+C for each attribute U.
  • Color assembly module 212 provides the attribute equations (EQS, which may include e.g., the plane-equation coefficients A, B and C for each primitive that covers at least one pixel and a list of screen coordinates (X,Y) of the covered pixels to a pixel module 224 in multithreaded core array 202. Pixel module 224 directs programmable processing engines (not explicitly shown) in multithreaded core array 202 to execute one or more pixel shader programs on each pixel covered by the primitive, with the program(s) being selected in response to the state information provided by front end 204. As with vertex shader programs and geometry shader programs, rendering applications can specify the pixel shader program to be used for any given set of pixels. Pixel shader programs can be used to implement a variety of visual effects, including lighting and shading effects, reflections, texture blending, procedural texture generation, and so on. Numerous examples of such per-pixel operations are known in the art and a detailed description is omitted as not being critical to understanding the present invention. Pixel shader programs can implement algorithms using a wide range of mathematical and logical operations on pixels and other data, and the programs can include conditional or branching execution paths and direct and indirect memory accesses.
  • Pixel shader programs are advantageously executed in multithreaded core array 202 using the same programmable processing engines that also execute the vertex and/or geometry shader programs. Thus, at certain times, a given processing engine may operate as a vertex shader, receiving and executing vertex program instructions; at other times the same processing engine may operates as a geometry shader, receiving and executing geometry program instructions; and at still other times the same processing engine may operate as a pixel shader, receiving and executing pixel shader program instructions. It will be appreciated that the multithreaded core array can provide natural load-balancing between pixel and vertex processing: where the application is geometry intensive (e.g., many small primitives), a larger fraction of the processing cycles in multithreaded core array 202 will tend to be devoted to vertex and/or geometry shaders, and where the application is pixel intensive (e.g., fewer and larger primitives shaded using complex pixel shader programs with multiple textures and the like), a larger fraction of the processing cycles will tend to be devoted to pixel shaders.
  • Once processing for a pixel or group of pixels is complete, pixel module 224 provides the processed pixels (PDATA) to ROP 214. ROP 214, which may be of generally conventional design, integrates the pixel values received from pixel module 224 with pixels of the image under construction in frame buffer 226, which may be located, e.g., in graphics memory 124. In some embodiments, ROP 214 can mask pixels or blend new pixels with pixels previously written to the rendered image. Depth buffers, alpha buffers, and stencil buffers can also be used to determine the contribution (if any) of each incoming pixel to the rendered image. Pixel data PDATA′ corresponding to the appropriate combination of each incoming pixel value and any previously stored pixel value is written back to frame buffer 226. Once the image is complete, frame buffer 226 can be scanned out to a display device and/or subjected to further processing.
  • It will be appreciated that the rendering pipeline described herein is illustrative and that variations and modifications are possible. The pipeline may include different units from those shown and the sequence of processing events may be varied from that described herein. For instance, in some embodiments, rasterization may be performed in stages, with a “coarse” rasterizer that processes the entire screen in blocks (e.g., 16×16 pixels) to determine which, if any, blocks the triangle covers (or partially covers), followed by a “fine” rasterizer that processes the individual pixels within any block that is determined to be at least partially covered. In one such embodiment, the fine rasterizer is contained within pixel module 224. In another embodiment, some operations conventionally performed by a ROP may be performed within pixel module 224 before the pixel data is forwarded to ROP 214.
  • Further, multiple instances of some or all of the modules described herein may be operated in parallel. In one such embodiment, multithreaded core array 202 includes two or more geometry modules 218 and an equal number of pixel modules 224 that operate in parallel. Each geometry module and pixel module jointly controls a different subset of the processing engines in multithreaded core array 202.
  • Multithreaded Core Array Configuration
  • In one embodiment, multithreaded core array 202 provides a highly parallel architecture that supports concurrent execution of a large number of instances of vertex, geometry, and/or pixel shader programs in various combinations. FIG. 3 is a block diagram of multithreaded core array 202 according to an embodiment of the present invention.
  • In this embodiment, multithreaded core array 202 includes some number (N) of processing clusters 302. Herein, multiple instances of like objects are denoted with reference numbers identifying the object and parenthetical numbers identifying the instance where needed. Any number N (e.g., 1, 4, 8, or any other number) of processing clusters may be provided. In FIG. 3, one processing cluster 302 is shown in detail; it is to be understood that other processing clusters 302 can be of similar or identical design.
  • Each processing cluster 302 includes a geometry controller 304 (implementing geometry module 218 of FIG. 2) and a pixel controller 306 (implementing pixel module 224 of FIG. 2). Geometry controller 304 and pixel controller 306 each communicate with a core interface 308. Core interface 308 controls a number (A) of cores 310 that include the processing engines of multithreaded core array 202. Any number M (e.g., 1, 2, 4 or any other number) of cores 310 may be connected to a single core interface. Each core 310 is advantageously implemented as a multithreaded execution core capable of supporting a large number (e.g., 100 or more) of concurrent execution threads (where the term “thread” refers to an instance of a particular program executing on a particular set of input data), including a combination of vertex threads, geometry threads, and pixel threads. In one embodiment, each core 310 implements a P-way SIMD architecture to execute P threads in parallel, where P is an arbitrary integer (e.g., 8, 16, 32) and is capable of managing a number G (e.g. 18, 24, etc.) of groups of P threads concurrently. A detailed description of core 310 can be found in U.S. Provisional Application No. 60/752,265, filed Dec. 19, 2005, which is incorporated herein by reference in its entirety for all purposes.
  • Core interface 308 also controls a texture pipeline 314 that is shared among cores 310. Texture pipeline 314, which may be of generally conventional design, advantageously includes logic circuits configured to receive texture coordinates, to fetch texture data corresponding to the texture coordinates from memory, and to filter the texture data according to various algorithms. Conventional filtering algorithms including bilinear and trilinear filtering may be used. When a core 310 encounters a texture instruction in one of its threads, it provides the texture coordinates to texture pipeline 314 via core interface 308. Texture pipeline 314 processes the texture instruction and returns the result to the core 310 via core interface 308. Texture processing by pipeline 314 may consume a significant number of clock cycles, and while a thread is waiting for the texture result, core 310 advantageously continues to execute other threads.
  • In operation, data assembler 206 (FIG. 2) provides geometry data GDATA to processing clusters 302. In one embodiment, data assembler 206 divides the incoming stream of geometry data into portions and selects, e.g., based on availability of execution resources, which of processing clusters 302 is to receive the next portion of the geometry data. That portion is delivered to geometry controller 304 in the selected processing cluster 302.
  • Geometry controller 304 forwards the received data to core interface 308, which loads the vertex data into a core 310, then instructs core 310 to launch the appropriate vertex shader program. Upon completion of the vertex shader program, core interface 308 signals geometry controller 304. If a geometry shader program is to be executed, geometry controller 304 instructs core interface 308 to launch the geometry shader program. In some embodiments, the processed vertex data is returned to geometry controller 304 upon completion of the vertex shader program, and geometry controller 304 instructs core interface 308 to reload the data before executing the geometry shader program. After completion of the vertex shader program and/or geometry shader program, geometry controller 304 provides the processed geometry data (GDATA′) to setup module 208 of FIG. 2.
  • At the pixel stage, color assembly module 212 (FIG. 2) provides attribute equations EQS for a primitive and pixel coordinates (X,Y) of pixels covered by the primitive to processing clusters 302. In one embodiment, color assembly module 212 divides the incoming stream of coverage data into portions and selects, e.g., based on availability of execution resources or the location of the primitive in screen coordinates, which of processing clusters 302 is to receive the next portion of the data. That portion is delivered to pixel controller 306 in the selected processing cluster 302.
  • Pixel controller 306 delivers the data to core interface 308, which loads the pixel data into a core 310, then instructs the core 310 to launch the pixel shader program. Where core 310 is multithreaded, pixel shader programs, geometry shader programs, and vertex shader programs can all be executed concurrently in the same core 310. Upon completion of the pixel shader program, core interface 308 delivers the processed pixel data to pixel controller 306, which forwards the pixel data PDATA to ROP unit 214 (FIG. 2).
  • It will be appreciated that the multithreaded core array described herein is illustrative and that variations and modifications are possible. Any number of processing clusters may be provided, and each processing cluster may include any number of cores. In some embodiments, shaders of certain types may be restricted to executing in certain processing clusters or in certain cores; for instance, geometry shaders might be restricted to executing in core 310(0) of each processing cluster. Such design choices may be driven by considerations of hardware size and complexity versus performance, as is known in the art. A shared texture pipeline is also optional; in some embodiments, each core might have its own texture pipeline or might leverage general-purpose functional units to perform texture computations.
  • Data to be processed can be distributed to the processing clusters in various ways. In one embodiment, the data assembler (or other source of geometry data) and color assembly module (or other source of pixel-shader input data) receive information indicating the availability of processing clusters or individual cores to handle additional threads of various types and select a destination processing cluster or core for each thread. In another embodiment, input data is forwarded from one processing cluster to the next until a processing cluster with capacity to process the data accepts it. In still another embodiment, processing clusters are selected based on properties of the input data, such as the screen coordinates of pixels to be processed.
  • The multithreaded core array can also be leveraged to perform general-purpose computations that might or might not be related to rendering images. In one embodiment, any computation that can be expressed in a data-parallel decomposition can be handled by the multithreaded core array as an array of threads executing in a single core. Results of such computations can be written to the frame buffer and read back into system memory.
  • Allocation of Pixel Shader Work
  • In accordance with an embodiment of the present invention, pixels to be processed by a pixel shader program are directed to a processing cluster 302 (FIG. 3) based on the position of the pixels within the image area. For example, the image area can be divided into a number of tiles. Each tile is associated with one of the processing clusters 302 in such a way that the tiles associated with one cluster are scattered across the image area (i.e., at least some of the tiles associated with one processing cluster are not contiguous with one another).
  • FIG. 4 illustrates one possible tiling of an image area 400 into a large number of tiles 402 according to an embodiment of the present invention. Each tile 402 might be, e.g., 16×16 pixels or any other convenient size. In this embodiment, multithreaded core array 202 of FIG. 3 includes eight processing clusters 302(0) through 302(7). Each tile 402 in FIG. 4 contains a number i (0 through 7) indicating which processing core 302(i) processes pixels in that tile. As can be seen in FIG. 4, each processing cluster 302 is assigned an equal (or nearly equal) number of tiles 402 within image area 400, and the tiles assigned to each cluster 302 are not contiguous with each other. It is expected that for many graphics applications, distributing work in this manner will provide approximate load balancing among the processing clusters 302. Suitable pixel distribution logic can be included in rendering pipeline 200, e.g., in color assembly module 212 of FIG. 2.
  • It will be appreciated that the tiling shown in FIG. 4 is illustrative and that variations and modifications are possible. The tiles may be of any size. In some embodiments, the size and number of tiles is configurable, with tile size being chosen based on application characteristics such as whether a multisampling mode is in use. The arrangement of tiles assigned to each processing cluster can vary as desired.
  • Tiles may be assigned to any number of processing clusters, up to the total number that are present in a particular GPU. In some embodiments, tiles are assigned to fewer than all of the processing clusters. Thus, a GPU can render images using only some of its processing clusters to process pixel threads. As long as at least one processing cluster is available, the GPU will be able to render images, albeit at reduced throughput. Running with some clusters disabled from processing pixel threads may be useful, e.g., for operating in a reduced-power mode (some cores or clusters can be powered down while others operate), for determining minimum performance requirements (without requiring the availability of different GPUs), and/or for providing tolerance against defects in one or another of the cores.
  • In some alternative embodiments, tiles are assigned to particular cores 310 rather than to processing clusters 302.
  • Pixel Shader Coupling to Frame Buffer
  • In some embodiments, rather than the centralized ROP 214 suggested in FIG. 2, each pixel controller 306 in FIG. 3 includes its own ROP that communicates pixels to frame buffer 226 of FIG. 2. In such embodiments, a coupling from processing clusters 302 to the frame buffer is provided.
  • In one embodiment with N processing clusters, frame buffer 226 is partitioned into N partitions. Each cluster 302 is coupled to a different one of the N partitions.
  • FIG. 5 is a simplified block diagram illustrating a coupling between processing clusters 302 and a frame buffer 500 according to an embodiment of the present invention. It is to be understood that frame buffer 226 of FIG. 2 might include multiple frame buffers 500, where each frame buffer 500 stores a specified quantity on a per-pixel basis for the same image. For instance, in one embodiment, frame buffer 226 includes a Z buffer; color component buffers (e.g., for red, green and blue color components); and a transparency (alpha) buffer. It is to be understood that any number of frame buffers 500 may be provided and that “pixel” as used herein refers to sampling locations within the image, which might or might not correspond to the number of active pixels in a given display device. For simplicity, only one frame buffer 500 is shown; it is to be understood that the same partitioning can be applied to each frame buffer for an image.
  • Frame buffer 500 is partitioned (physically or logically) into N partitions 502, with each partition being large enough to store the data for at least 1/N of the pixels in the image. Each of the N processing clusters 302 is coupled to one of the N partitions 502. Thus, processing cluster 302(0) stores all of its output pixel data in partition 502(0), processing cluster 302(1) in partition 502(1) and so on. It should be noted that to the extent that tiles processed by a given processing cluster 302 are not contiguous, the data in a given frame buffer partition 502 will be from non-contiguous tiles. The display (scanout) logic advantageously observes the correct display ordering of the data when accessing frame buffer 500; in particular, it is not required that partitions be read out sequentially.
  • As noted above, in some embodiments, fewer than all of processing cores 302 might be used to generate pixels. In the embodiment shown in FIG. 5, only processing cluster 302(0) provides pixels to frame buffer partition 502(0). Accordingly, if processing cluster 302(0) is not operated to generate pixels, frame buffer partition 502(0) will not be used. The image area can be retiled or tiles can be reassigned among processing clusters 302(1) through 302(N−1) such that the area is divided among N−1 processing clusters. In some embodiments, the sampling resolution might need to be reduced, e.g., if frame buffer partitions 502(1) through 502(N−1) do not provide enough space to store all of the pixel data for the image at the original sampling resolution. In embodiments where the partitions are logical rather than physical, frame buffer 500 can be repartitioned to match the number of processing clusters 302 available.
  • In an alternative embodiment, each processing cluster can access multiple frame buffer partitions. FIG. 6 is a simplified block diagram illustrating a coupling between processing clusters 302 and a frame buffer 600 according to an embodiment of the present invention. It is to be understood that frame buffer 226 of FIG. 2 might include multiple frame buffers 600, where each frame buffer 600 stores a specified quantity on a per-pixel basis for the same image as described above with reference to frame buffer 500. It is to be understood that any number of frame buffers 600 may be provided. For simplicity, only one frame buffer 600 is shown; it is to be understood that the partitioning can be applied to each frame buffer for an image.
  • Frame buffer 600 is partitioned (physically or logically) into a number B of partitions 602, where B might be equal to or different from the number N of processing clusters 302. Processing clusters 302 are coupled to partitions 602 via a crossbar 604. Each cluster 302 can write pixel data to any one (or more) of the B partitions 602.
  • In this embodiment, crossbar 604 is configurable, allowing the coupling of processing clusters 302 to frame buffer partitions 602 to be modified as desired. For example, as noted above, in some embodiments, fewer than all of processing cores 302 might be used to generate pixels. In the embodiment shown in FIG. 6, if processing core 302(0) is disabled, crossbar 604 can be reconfigured so that all frame buffer partitions 602 are still accessible to one or another of processing cores 302. The display (scanout) logic is advantageously configurable such that the frame buffer data is correctly scanned out regardless of the configuration of crossbar 604 or the assignment of tiles to processing cores 302.
  • Where multiple frame buffers are present (e.g., Z, color, alpha, etc.), each frame buffer may be partitioned into B partitions in the manner described. In some embodiments, the number of partitions is not the same for all frame buffers; for instance, a Z buffer might have more or fewer partitions than a color buffer.
  • Further Embodiments
  • While the invention has been described with respect to specific embodiments, one skilled in the art will recognize that numerous modifications are possible. Thus, although the invention has been described with respect to specific embodiments, it will be appreciated that the invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims (7)

1. A graphics processor comprising:
a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data;
a rasterizer configured to generate coverage data for each of a plurality of pixels; and
pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array,
wherein the pixel distribution logic selects the one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area.
2. The graphics processor of claim 1 wherein the image area is divided into a plurality of tiles, each tile being assigned to one of the processing clusters, and wherein the pixel distribution logic selects the one of the processing clusters based on a determination as to which of the plurality of tiles includes the first pixel.
3. The graphics processor of claim 2 wherein at least two of the plurality of tiles are assigned to each of the processing clusters, wherein for each processing cluster, the tiles assigned thereto are not contiguous with each other.
4. The graphics processor of claim 1 wherein each of the processing clusters is configured to deliver pixel data to a respective one of a plurality of partitions of a frame buffer.
5. The graphics processor of claim 1 further comprising a crossbar coupled to each of the processing clusters and configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
6. The graphics processor of claim 5 wherein the crossbar is configured such that pixel data generated by any one of the processing clusters is deliverable to any one of the frame buffer partitions.
7. The graphics processor of claim 1 wherein each processing core is also operable to execute vertex shader programs and geometry shader programs.
US11/611,745 2005-12-19 2006-12-15 Parallel Array Architecture for a Graphics Processor Abandoned US20070159488A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/611,745 US20070159488A1 (en) 2005-12-19 2006-12-15 Parallel Array Architecture for a Graphics Processor
US13/269,462 US8730249B2 (en) 2005-12-19 2011-10-07 Parallel array architecture for a graphics processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75226505P 2005-12-19 2005-12-19
US11/611,745 US20070159488A1 (en) 2005-12-19 2006-12-15 Parallel Array Architecture for a Graphics Processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/269,462 Continuation US8730249B2 (en) 2005-12-19 2011-10-07 Parallel array architecture for a graphics processor

Publications (1)

Publication Number Publication Date
US20070159488A1 true US20070159488A1 (en) 2007-07-12

Family

ID=38541600

Family Applications (4)

Application Number Title Priority Date Filing Date
US11/446,046 Active 2028-05-24 US7728841B1 (en) 2005-12-19 2006-06-01 Coherent shader output for multiple targets
US11/611,745 Abandoned US20070159488A1 (en) 2005-12-19 2006-12-15 Parallel Array Architecture for a Graphics Processor
US11/612,415 Active 2029-08-18 US7830392B1 (en) 2005-12-19 2006-12-18 Connecting multiple pixel shaders to a frame buffer without a crossbar
US13/269,462 Active US8730249B2 (en) 2005-12-19 2011-10-07 Parallel array architecture for a graphics processor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11/446,046 Active 2028-05-24 US7728841B1 (en) 2005-12-19 2006-06-01 Coherent shader output for multiple targets

Family Applications After (2)

Application Number Title Priority Date Filing Date
US11/612,415 Active 2029-08-18 US7830392B1 (en) 2005-12-19 2006-12-18 Connecting multiple pixel shaders to a frame buffer without a crossbar
US13/269,462 Active US8730249B2 (en) 2005-12-19 2011-10-07 Parallel array architecture for a graphics processor

Country Status (8)

Country Link
US (4) US7728841B1 (en)
JP (2) JP2009520307A (en)
KR (1) KR101027621B1 (en)
CN (1) CN101371247B (en)
DE (1) DE112006003473B4 (en)
GB (1) GB2446546B (en)
TW (1) TWI368182B (en)
WO (1) WO2007111743A2 (en)

Cited By (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070291040A1 (en) * 2005-01-25 2007-12-20 Reuven Bakalash Multi-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operation
US20080010754A1 (en) * 2006-07-12 2008-01-17 The Procter & Gamble Company Gel network surfactant based thickening systems for hair colourant and bleaching compositions
US20080068389A1 (en) * 2003-11-19 2008-03-20 Reuven Bakalash Multi-mode parallel graphics rendering system (MMPGRS) embodied within a host computing system and employing the profiling of scenes in graphics-based applications
US20080094403A1 (en) * 2003-11-19 2008-04-24 Reuven Bakalash Computing system capable of parallelizing the operation graphics processing units (GPUs) supported on a CPU/GPU fusion-architecture chip and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US20080129741A1 (en) * 2004-01-28 2008-06-05 Lucid Information Technology, Ltd. PC-based computing system employing a bridge chip having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
US20080165184A1 (en) * 2003-11-19 2008-07-10 Reuven Bakalash PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US20080170082A1 (en) * 2007-01-17 2008-07-17 Samsung Electronics Co., Ltd. Graphics engine and method of distributing pixel data
US20090096798A1 (en) * 2005-01-25 2009-04-16 Reuven Bakalash Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
US20090132878A1 (en) * 2007-11-15 2009-05-21 Garland Michael J System, method, and computer program product for performing a scan operation on a sequence of single-bit values using a parallel processor architecture
US20100149195A1 (en) * 2008-12-15 2010-06-17 Canon Kabushiki Kaisha Load balancing in multiple processor rendering systems
US20100277488A1 (en) * 2009-04-30 2010-11-04 Kevin Myers Deferred Material Rasterization
US20110095941A1 (en) * 2009-10-26 2011-04-28 Metron Aviation, Inc. Cell clustering and optimization for space partitioning
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US20110153984A1 (en) * 2009-12-21 2011-06-23 Andrew Wolfe Dynamic voltage change for multi-core processing
US20110187712A1 (en) * 2010-02-01 2011-08-04 Samsung Electronics Co., Ltd. Parallel operation processing apparatus and method
US8065288B1 (en) 2007-11-09 2011-11-22 Nvidia Corporation System, method, and computer program product for testing a query against multiple sets of objects utilizing a single instruction multiple data (SIMD) processing architecture
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US20120019541A1 (en) * 2010-07-20 2012-01-26 Advanced Micro Devices, Inc. Multi-Primitive System
US20120096474A1 (en) * 2010-10-15 2012-04-19 Via Technologies, Inc. Systems and Methods for Performing Multi-Program General Purpose Shader Kickoff
US8243083B1 (en) 2007-12-04 2012-08-14 Nvidia Corporation System, method, and computer program product for converting a scan algorithm to a segmented scan algorithm in an operator-independent manner
US8264484B1 (en) 2007-10-29 2012-09-11 Nvidia Corporation System, method, and computer program product for organizing a plurality of rays utilizing a bounding volume
US8271734B1 (en) * 2008-12-05 2012-09-18 Nvidia Corporation Method and system for converting data formats using a shared cache coupled between clients and an external memory
US8284207B2 (en) 2003-11-19 2012-10-09 Lucid Information Technology, Ltd. Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US8284188B1 (en) 2007-10-29 2012-10-09 Nvidia Corporation Ray tracing system, method, and computer program product for simultaneously traversing a hierarchy of rays and a hierarchy of objects
US8321492B1 (en) * 2008-12-11 2012-11-27 Nvidia Corporation System, method, and computer program product for converting a reduction algorithm to a segmented reduction algorithm
US8497865B2 (en) 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US20130267835A1 (en) * 2012-04-10 2013-10-10 Jerome Ranjeev Edwards System and method for localizing medical instruments during cardiovascular medical procedures
US20130342549A1 (en) * 2012-06-26 2013-12-26 Samsung Electronics Co., Ltd. Apparatus and method for processing rendering data
US8773422B1 (en) 2007-12-04 2014-07-08 Nvidia Corporation System, method, and computer program product for grouping linearly ordered primitives
CN104050618A (en) * 2013-03-15 2014-09-17 辉达公司 Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US20140281383A1 (en) * 2013-03-15 2014-09-18 Nvidia Corporation Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US20140267276A1 (en) * 2013-03-15 2014-09-18 Nvidia Corporation System, method, and computer program product for generating primitive specific attributes
US8947444B1 (en) * 2008-12-09 2015-02-03 Nvidia Corporation Distributed vertex attribute fetch
US8996846B2 (en) 2007-09-27 2015-03-31 Nvidia Corporation System, method and computer program product for performing a scan operation
GB2521151A (en) * 2013-12-10 2015-06-17 Advanced Risc Mach Ltd Configurable thread ordering for a data processing apparatus
US9071244B2 (en) 2012-01-26 2015-06-30 Nvidia Corporation Ground referenced single-ended signaling
US9147447B2 (en) 2013-03-15 2015-09-29 Nvidia Corporation Ground-referenced single-ended memory interconnect
US9153314B2 (en) 2013-03-15 2015-10-06 Nvidia Corporation Ground-referenced single-ended memory interconnect
US9171607B2 (en) 2013-03-15 2015-10-27 Nvidia Corporation Ground-referenced single-ended system-on-package
US9338036B2 (en) 2012-01-30 2016-05-10 Nvidia Corporation Data-driven charge-pump transmitter for differential signaling
US9498143B2 (en) 2013-08-22 2016-11-22 Aftx, Inc. Methods, systems, and apparatus for identification and characterization of rotors associated with atrial fibrillation
US9721320B2 (en) 2012-03-09 2017-08-01 Nvidia Corporation Fully parallel in-place construction of 3D acceleration structures and bounding volume hierarchies in a graphics processing unit
US20180082470A1 (en) * 2016-09-22 2018-03-22 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
WO2018151981A1 (en) * 2017-02-15 2018-08-23 Microsoft Technology Licensing, Llc Multiple shader processes in graphics processing
US10204394B2 (en) * 2017-04-10 2019-02-12 Intel Corporation Multi-frame renderer
US20190221154A1 (en) * 2014-09-30 2019-07-18 Microsoft Technology Licensing, Llc Displaying content on a display in power save mode
US10482564B2 (en) 2016-09-12 2019-11-19 Alibaba Group Holding Limited Method and system for improving GPU performance during data-intensive visualization operations
EP3553750A4 (en) * 2016-12-09 2020-06-10 Sony Interactive Entertainment Inc. Image processing device, image processing method, and program
US10733012B2 (en) 2013-12-10 2020-08-04 Arm Limited Configuring thread scheduling on a multi-threaded data processing apparatus
US10847117B1 (en) * 2019-05-13 2020-11-24 Adobe Inc. Controlling an augmented reality display with transparency control using multiple sets of video buffers
CN114463160A (en) * 2022-01-30 2022-05-10 摩尔线程智能科技(北京)有限责任公司 Parallel processing method and device for graphics pipeline and readable storage medium
WO2022251333A3 (en) * 2021-05-28 2023-01-19 MemComputing, Inc. Memory graphics processing unit
US11626058B2 (en) * 2020-09-09 2023-04-11 Samsung Display Co., Ltd. Display apparatus and method of driving the same
CN116263981A (en) * 2022-04-20 2023-06-16 象帝先计算技术(重庆)有限公司 Graphics processor, system, apparatus, device, and method
US20230196652A1 (en) * 2021-03-05 2023-06-22 Ideapool Technology Co., Ltd. A three-dimensional image player capable of real-time interaction

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8190669B1 (en) 2004-10-20 2012-05-29 Nvidia Corporation Multipurpose arithmetic functional unit
US8051123B1 (en) 2006-12-15 2011-11-01 Nvidia Corporation Multipurpose functional unit with double-precision and filtering operations
US8106914B2 (en) 2007-12-07 2012-01-31 Nvidia Corporation Fused multiply-add functional unit
US9678775B1 (en) * 2008-04-09 2017-06-13 Nvidia Corporation Allocating memory for local variables of a multi-threaded program for execution in a single-threaded environment
US8274516B2 (en) * 2008-08-04 2012-09-25 Microsoft Corporation GPU scene composition and animation
US8619087B2 (en) * 2009-10-06 2013-12-31 Nvidia Corporation Inter-shader attribute buffer optimization
US8704732B2 (en) * 2010-09-29 2014-04-22 Qualcomm Incorporated Image synchronization for multiple displays
KR101799978B1 (en) 2011-06-17 2017-11-22 삼성전자주식회사 Method and apparatus for tile based rendering using tile-to-tile locality
US9092267B2 (en) * 2011-06-20 2015-07-28 Qualcomm Incorporated Memory sharing in graphics processing unit
US8752018B2 (en) * 2011-06-21 2014-06-10 Nvidia Corporation Emitting coherent output from multiple threads for printf
CN103136724B (en) * 2011-11-30 2015-11-25 北大方正集团有限公司 screening method and device
US10740254B2 (en) * 2012-01-03 2020-08-11 Nvidia Corporation System and method for frame buffer copy during partial power down of memory
JP5949188B2 (en) 2012-06-08 2016-07-06 日本電気株式会社 Tightly coupled multiprocessor system
US9104421B2 (en) * 2012-07-30 2015-08-11 Nvidia Corporation Training, power-gating, and dynamic frequency changing of a memory controller
US9165399B2 (en) * 2012-11-01 2015-10-20 Nvidia Corporation System, method, and computer program product for inputting modified coverage data into a pixel shader
US20140192052A1 (en) * 2013-01-09 2014-07-10 Advanced Micro Devices, Inc. 2d rendering on 3d graphics hardware
US9292898B2 (en) * 2013-03-15 2016-03-22 Intel Corporation Conditional end of thread mechanism
US9501859B2 (en) * 2013-07-19 2016-11-22 Adobe Systems Incorporated Triangle rasterization
KR102111740B1 (en) * 2014-04-03 2020-05-15 삼성전자주식회사 Method and device for processing image data
US10068311B2 (en) * 2014-04-05 2018-09-04 Sony Interacive Entertainment LLC Varying effective resolution by screen location by changing active color sample count within multiple render targets
US11302054B2 (en) 2014-04-05 2022-04-12 Sony Interactive Entertainment Europe Limited Varying effective resolution by screen location by changing active color sample count within multiple render targets
US10783696B2 (en) 2014-04-05 2020-09-22 Sony Interactive Entertainment LLC Gradient adjustment for texture mapping to non-orthonormal grid
US9710881B2 (en) 2014-04-05 2017-07-18 Sony Interactive Entertainment America Llc Varying effective resolution by screen location by altering rasterization parameters
US9928564B2 (en) * 2014-06-26 2018-03-27 Intel Corporation Efficient hardware mechanism to ensure shared resource data coherency across draw calls
US20160093069A1 (en) * 2014-09-26 2016-03-31 Subramaniam Maiyuran Method and apparatus for pixel hashing
US9684950B2 (en) * 2014-12-18 2017-06-20 Qualcomm Incorporated Vision correction through graphics processing
US10013735B2 (en) * 2015-01-28 2018-07-03 Qualcomm Incorporated Graphics processing unit with bayer mapping
US10319348B2 (en) 2015-05-11 2019-06-11 Vixs Systems, Inc. Memory subsystem consumer trigger
US20160335734A1 (en) * 2015-05-11 2016-11-17 Vixs Systems, Inc. Memory subsystem synchronization primitives
US10768935B2 (en) * 2015-10-29 2020-09-08 Intel Corporation Boosting local memory performance in processor graphics
US10552211B2 (en) * 2016-09-02 2020-02-04 Intel Corporation Mechanism to increase thread parallelism in a graphics processor
US11379941B2 (en) * 2016-09-22 2022-07-05 Advanced Micro Devices, Inc. Primitive shader
CN107977227A (en) 2016-10-21 2018-05-01 超威半导体公司 The pipeline of separate hardware data path including different instruction type
US10417731B2 (en) 2017-04-24 2019-09-17 Intel Corporation Compute optimization mechanism for deep neural networks
US10417734B2 (en) 2017-04-24 2019-09-17 Intel Corporation Compute optimization mechanism for deep neural networks
US10257487B1 (en) 2018-01-16 2019-04-09 Qualcomm Incorporated Power efficient video playback based on display hardware feedback
US10409359B2 (en) * 2018-01-17 2019-09-10 Qualcomm Incorporated Dynamic bin ordering for load synchronization
US10698392B2 (en) * 2018-06-22 2020-06-30 Applied Materials, Inc. Using graphics processing unit for substrate routing and throughput modeling
US20210272347A1 (en) * 2020-02-28 2021-09-02 Advanced Micro Devices, Inc. Fully utilized hardware in a multi-tenancy graphics processing unit

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408646A (en) * 1991-03-29 1995-04-18 International Business Machines Corp. Multipath torus switching apparatus
US5408606A (en) * 1993-01-07 1995-04-18 Evans & Sutherland Computer Corp. Computer graphics system with parallel processing using a switch structure
US5794016A (en) * 1995-12-11 1998-08-11 Dynamic Pictures, Inc. Parallel-processor graphics architecture
US20020174318A1 (en) * 1999-04-09 2002-11-21 Dave Stuttard Parallel data processing apparatus
US6853380B2 (en) * 2002-03-04 2005-02-08 Hewlett-Packard Development Company, L.P. Graphical display system and method
US20050093873A1 (en) * 2003-10-29 2005-05-05 Timour Paltashev Apparatus for compressing data in a bit stream or bit pattern
US20050219253A1 (en) * 2004-03-31 2005-10-06 Piazza Thomas A Render-cache controller for multithreading, multi-core graphics processor
US20060161757A1 (en) * 2004-12-23 2006-07-20 Intel Corporation Dynamic allocation of a buffer across multiple clients in a threaded processor
US7161603B2 (en) * 2003-04-28 2007-01-09 Kabushiki Kaisha Toshiba Image rendering device and image rendering method
US7233331B2 (en) * 2000-03-16 2007-06-19 Square Enix Co., Ltd. Parallel object task engine and processing method
US20080198167A1 (en) * 2003-11-19 2008-08-21 Reuven Bakalash Computing system capable of parallelizing the operation of graphics processing units (GPUS) supported on an integrated graphics device (IGD) and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US7570267B2 (en) * 2004-05-03 2009-08-04 Microsoft Corporation Systems and methods for providing an enhanced graphics pipeline

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US6181355B1 (en) * 1998-07-17 2001-01-30 3Dlabs Inc. Ltd. Graphics processing with transcendental function generator
US6693719B1 (en) * 1998-09-16 2004-02-17 Texas Instruments Incorporated Path to trapezoid decomposition of polygons for printing files in a page description language
US6636222B1 (en) * 1999-11-09 2003-10-21 Broadcom Corporation Video and graphics system with an MPEG video decoder for concurrent multi-row decoding
US6924807B2 (en) * 2000-03-23 2005-08-02 Sony Computer Entertainment Inc. Image processing apparatus and method
US7184059B1 (en) * 2000-08-23 2007-02-27 Nintendo Co., Ltd. Graphics system with copy out conversions between embedded frame buffer and main memory
US20030234749A1 (en) * 2002-06-20 2003-12-25 Johnny Marks System and method for communicating graphics image data over a communication network for display on a single logical screen
US7075542B1 (en) * 2002-11-12 2006-07-11 Ati Technologies Inc. Selectable multi-performance configuration
US7633506B1 (en) * 2002-11-27 2009-12-15 Ati Technologies Ulc Parallel pipeline graphics system
US20050231533A1 (en) * 2004-04-20 2005-10-20 Lin Chen Apparatus and method for performing divide by w operations in a graphics system
US7154500B2 (en) * 2004-04-20 2006-12-26 The Chinese University Of Hong Kong Block-based fragment filtration with feasible multi-GPU acceleration for real-time volume rendering on conventional personal computer
US7978205B1 (en) * 2004-05-03 2011-07-12 Microsoft Corporation Systems and methods for providing an enhanced graphics pipeline

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408646A (en) * 1991-03-29 1995-04-18 International Business Machines Corp. Multipath torus switching apparatus
US5408606A (en) * 1993-01-07 1995-04-18 Evans & Sutherland Computer Corp. Computer graphics system with parallel processing using a switch structure
US5794016A (en) * 1995-12-11 1998-08-11 Dynamic Pictures, Inc. Parallel-processor graphics architecture
US20020174318A1 (en) * 1999-04-09 2002-11-21 Dave Stuttard Parallel data processing apparatus
US7233331B2 (en) * 2000-03-16 2007-06-19 Square Enix Co., Ltd. Parallel object task engine and processing method
US6853380B2 (en) * 2002-03-04 2005-02-08 Hewlett-Packard Development Company, L.P. Graphical display system and method
US7161603B2 (en) * 2003-04-28 2007-01-09 Kabushiki Kaisha Toshiba Image rendering device and image rendering method
US20050093873A1 (en) * 2003-10-29 2005-05-05 Timour Paltashev Apparatus for compressing data in a bit stream or bit pattern
US20080198167A1 (en) * 2003-11-19 2008-08-21 Reuven Bakalash Computing system capable of parallelizing the operation of graphics processing units (GPUS) supported on an integrated graphics device (IGD) and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US20050219253A1 (en) * 2004-03-31 2005-10-06 Piazza Thomas A Render-cache controller for multithreading, multi-core graphics processor
US7570267B2 (en) * 2004-05-03 2009-08-04 Microsoft Corporation Systems and methods for providing an enhanced graphics pipeline
US20060161757A1 (en) * 2004-12-23 2006-07-20 Intel Corporation Dynamic allocation of a buffer across multiple clients in a threaded processor

Cited By (124)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8754894B2 (en) 2003-11-19 2014-06-17 Lucidlogix Software Solutions, Ltd. Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications
US20080074428A1 (en) * 2003-11-19 2008-03-27 Reuven Bakalash Method of rendering pixel-composited images for a graphics-based application running on a computing system embodying a multi-mode parallel graphics rendering system
US20080068389A1 (en) * 2003-11-19 2008-03-20 Reuven Bakalash Multi-mode parallel graphics rendering system (MMPGRS) embodied within a host computing system and employing the profiling of scenes in graphics-based applications
US8125487B2 (en) 2003-11-19 2012-02-28 Lucid Information Technology, Ltd Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board
US20080074429A1 (en) * 2003-11-19 2008-03-27 Reuven Bakalash Multi-mode parallel graphics rendering system (MMPGRS) supporting real-time transition between multiple states of parallel rendering operation in response to the automatic detection of predetermined operating conditions
US20080079737A1 (en) * 2003-11-19 2008-04-03 Reuven Bakalash Multi-mode parallel graphics rendering and display system supporting real-time detection of mode control commands (MCCS) programmed within pre-profiled scenes of the graphics-based application
US20080084421A1 (en) * 2003-11-19 2008-04-10 Reuven Bakalash Computing system capable of parallelizing the operation of multiple graphical processing units (GPUs) supported on external graphics cards, with image recomposition being carried out within said GPUs
US20080084419A1 (en) * 2003-11-19 2008-04-10 Reuven Bakalash Computing system capable of parallelizing the operation of multiple graphics processing units supported on external graphics cards connected to a graphics hub device
US20080084418A1 (en) * 2003-11-19 2008-04-10 Reuven Bakalash Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on an integrated graphics device (IGD) within a bridge circuit
US20080084423A1 (en) * 2003-11-19 2008-04-10 Reuven Bakalash Computing system capable of parallelizing the operation of multiple graphics pipelines (GPPLS) implemented on a multi-core CPU chip
US20080198167A1 (en) * 2003-11-19 2008-08-21 Reuven Bakalash Computing system capable of parallelizing the operation of graphics processing units (GPUS) supported on an integrated graphics device (IGD) and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US20080088632A1 (en) * 2003-11-19 2008-04-17 Reuven Bakalash Computing system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on an integrated graphics device (IGD) within a bridge circuit, wherewithin image recomposition is carried out
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US20080094402A1 (en) * 2003-11-19 2008-04-24 Reuven Bakalash Computing system having a parallel graphics rendering system employing multiple graphics processing pipelines (GPPLS) dynamically controlled according to time, image and object division modes of parallel operation during the run-time of graphics-based applications running on the computing system
US20080100630A1 (en) * 2003-11-19 2008-05-01 Reuven Bakalash Game console system capable of paralleling the operation of multiple graphics processing units (GPUs) employing using a graphics hub device supported on a game console board
US8134563B2 (en) 2003-11-19 2012-03-13 Lucid Information Technology, Ltd Computing system having multi-mode parallel graphics rendering subsystem (MMPGRS) employing real-time automatic scene profiling and mode control
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US7944450B2 (en) 2003-11-19 2011-05-17 Lucid Information Technology, Ltd. Computing system having a hybrid CPU/GPU fusion-type graphics processing pipeline (GPPL) architecture
US20080165184A1 (en) * 2003-11-19 2008-07-10 Reuven Bakalash PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US9584592B2 (en) 2003-11-19 2017-02-28 Lucidlogix Technologies Ltd. Internet-based graphics application profile management system for updating graphic application profiles stored within the multi-GPU graphics rendering subsystems of client machines running graphics-based applications
US20080084422A1 (en) * 2003-11-19 2008-04-10 Reuven Bakalash Computing system capable of parallelizing the operation of multiple graphics processing units (GPUS) supported on external graphics cards connected to a graphics hub device with image recomposition being carried out across two or more of said GPUS
US9405586B2 (en) 2003-11-19 2016-08-02 Lucidlogix Technologies, Ltd. Method of dynamic load-balancing within a PC-based computing system employing a multiple GPU-based graphics pipeline architecture supporting multiple modes of GPU parallelization
US20080094403A1 (en) * 2003-11-19 2008-04-24 Reuven Bakalash Computing system capable of parallelizing the operation graphics processing units (GPUs) supported on a CPU/GPU fusion-architecture chip and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
US7940274B2 (en) 2003-11-19 2011-05-10 Lucid Information Technology, Ltd Computing system having a multiple graphics processing pipeline (GPPL) architecture supported on multiple external graphics cards connected to an integrated graphics device (IGD) embodied within a bridge circuit
US7777748B2 (en) 2003-11-19 2010-08-17 Lucid Information Technology, Ltd. PC-level computing system with a multi-mode parallel graphics rendering subsystem employing an automatic mode controller, responsive to performance data collected during the run-time of graphics applications
US7796129B2 (en) 2003-11-19 2010-09-14 Lucid Information Technology, Ltd. Multi-GPU graphics processing subsystem for installation in a PC-based computing system having a central processing unit (CPU) and a PC bus
US7796130B2 (en) 2003-11-19 2010-09-14 Lucid Information Technology, Ltd. PC-based computing system employing multiple graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware hub, and parallelized according to the object division mode of parallel operation
US7800619B2 (en) 2003-11-19 2010-09-21 Lucid Information Technology, Ltd. Method of providing a PC-based computing system with parallel graphics processing capabilities
US7800611B2 (en) 2003-11-19 2010-09-21 Lucid Information Technology, Ltd. Graphics hub subsystem for interfacing parallalized graphics processing units (GPUs) with the central processing unit (CPU) of a PC-based computing system having an CPU interface module and a PC bus
US7800610B2 (en) 2003-11-19 2010-09-21 Lucid Information Technology, Ltd. PC-based computing system employing a multi-GPU graphics pipeline architecture supporting multiple modes of GPU parallelization dymamically controlled while running a graphics application
US7808499B2 (en) 2003-11-19 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
US8284207B2 (en) 2003-11-19 2012-10-09 Lucid Information Technology, Ltd. Method of generating digital images of objects in 3D scenes while eliminating object overdrawing within the multiple graphics processing pipeline (GPPLS) of a parallel graphics processing system generating partial color-based complementary-type images along the viewing direction using black pixel rendering and subsequent recompositing operations
US7843457B2 (en) 2003-11-19 2010-11-30 Lucid Information Technology, Ltd. PC-based computing systems employing a bridge chip having a routing unit for distributing geometrical data and graphics commands to parallelized GPU-driven pipeline cores supported on a plurality of graphics cards and said bridge chip during the running of a graphics application
US8629877B2 (en) 2003-11-19 2014-01-14 Lucid Information Technology, Ltd. Method of and system for time-division based parallelization of graphics processing units (GPUs) employing a hardware hub with router interfaced between the CPU and the GPUs for the transfer of geometric data and graphics commands and rendered pixel data within the system
US7812846B2 (en) 2003-11-19 2010-10-12 Lucid Information Technology, Ltd PC-based computing system employing a silicon chip of monolithic construction having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
US7812845B2 (en) 2004-01-28 2010-10-12 Lucid Information Technology, Ltd. PC-based computing system employing a silicon chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
US7834880B2 (en) 2004-01-28 2010-11-16 Lucid Information Technology, Ltd. Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US7812844B2 (en) 2004-01-28 2010-10-12 Lucid Information Technology, Ltd. PC-based computing system employing a silicon chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallel operation during the running of a graphics application
US7808504B2 (en) 2004-01-28 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system having an integrated graphics subsystem supporting parallel graphics processing operations across a plurality of different graphics processing units (GPUS) from the same or different vendors, in a manner transparent to graphics applications
US8754897B2 (en) 2004-01-28 2014-06-17 Lucidlogix Software Solutions, Ltd. Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
US20080129743A1 (en) * 2004-01-28 2008-06-05 Reuven Bakalash Silicon chip of monolithic construction for integration in a PC-based computing system and having multiple GPU-driven pipeline cores supporting multiple modes of parallelization dynamically controlled while running a graphics application
US20080129742A1 (en) * 2004-01-28 2008-06-05 Reuven Bakalash PC-based computing system employing a bridge chip having a routing unit and a control unit for parallelizing multiple GPU-driven pipeline cores during the running of a graphics application
US20080129741A1 (en) * 2004-01-28 2008-06-05 Lucid Information Technology, Ltd. PC-based computing system employing a bridge chip having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
US9659340B2 (en) 2004-01-28 2017-05-23 Lucidlogix Technologies Ltd Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
US20090096798A1 (en) * 2005-01-25 2009-04-16 Reuven Bakalash Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
US11341602B2 (en) 2005-01-25 2022-05-24 Google Llc System on chip having processing and graphics units
US10614545B2 (en) 2005-01-25 2020-04-07 Google Llc System on chip having processing and graphics units
US10867364B2 (en) 2005-01-25 2020-12-15 Google Llc System on chip having processing and graphics units
US20070291040A1 (en) * 2005-01-25 2007-12-20 Reuven Bakalash Multi-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operation
US20080010754A1 (en) * 2006-07-12 2008-01-17 The Procter & Gamble Company Gel network surfactant based thickening systems for hair colourant and bleaching compositions
US8497865B2 (en) 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US20080170082A1 (en) * 2007-01-17 2008-07-17 Samsung Electronics Co., Ltd. Graphics engine and method of distributing pixel data
US8189007B2 (en) * 2007-01-17 2012-05-29 Samsung Electronics Co., Ltd. Graphics engine and method of distributing pixel data
US8996846B2 (en) 2007-09-27 2015-03-31 Nvidia Corporation System, method and computer program product for performing a scan operation
US8264484B1 (en) 2007-10-29 2012-09-11 Nvidia Corporation System, method, and computer program product for organizing a plurality of rays utilizing a bounding volume
US8284188B1 (en) 2007-10-29 2012-10-09 Nvidia Corporation Ray tracing system, method, and computer program product for simultaneously traversing a hierarchy of rays and a hierarchy of objects
US8065288B1 (en) 2007-11-09 2011-11-22 Nvidia Corporation System, method, and computer program product for testing a query against multiple sets of objects utilizing a single instruction multiple data (SIMD) processing architecture
US8661226B2 (en) 2007-11-15 2014-02-25 Nvidia Corporation System, method, and computer program product for performing a scan operation on a sequence of single-bit values using a parallel processor architecture
US20090132878A1 (en) * 2007-11-15 2009-05-21 Garland Michael J System, method, and computer program product for performing a scan operation on a sequence of single-bit values using a parallel processor architecture
US8773422B1 (en) 2007-12-04 2014-07-08 Nvidia Corporation System, method, and computer program product for grouping linearly ordered primitives
US8243083B1 (en) 2007-12-04 2012-08-14 Nvidia Corporation System, method, and computer program product for converting a scan algorithm to a segmented scan algorithm in an operator-independent manner
US8271734B1 (en) * 2008-12-05 2012-09-18 Nvidia Corporation Method and system for converting data formats using a shared cache coupled between clients and an external memory
US8947444B1 (en) * 2008-12-09 2015-02-03 Nvidia Corporation Distributed vertex attribute fetch
US8321492B1 (en) * 2008-12-11 2012-11-27 Nvidia Corporation System, method, and computer program product for converting a reduction algorithm to a segmented reduction algorithm
AU2008258132B2 (en) * 2008-12-15 2011-11-10 Canon Kabushiki Kaisha Load balancing in multiple processor rendering systems
US8704838B2 (en) 2008-12-15 2014-04-22 Canon Kabushiki Kaisha Load balancing in multiple processor rendering systems
US20100149195A1 (en) * 2008-12-15 2010-06-17 Canon Kabushiki Kaisha Load balancing in multiple processor rendering systems
US20100277488A1 (en) * 2009-04-30 2010-11-04 Kevin Myers Deferred Material Rasterization
US20110095941A1 (en) * 2009-10-26 2011-04-28 Metron Aviation, Inc. Cell clustering and optimization for space partitioning
US8259007B2 (en) * 2009-10-26 2012-09-04 Metron Aviation, Inc. Cell clustering and optimization for space partitioning
US20110153984A1 (en) * 2009-12-21 2011-06-23 Andrew Wolfe Dynamic voltage change for multi-core processing
US20110187712A1 (en) * 2010-02-01 2011-08-04 Samsung Electronics Co., Ltd. Parallel operation processing apparatus and method
US8692831B2 (en) 2010-02-01 2014-04-08 Samsung Electronics Co., Ltd. Parallel operation processing apparatus and method
US20120019541A1 (en) * 2010-07-20 2012-01-26 Advanced Micro Devices, Inc. Multi-Primitive System
US20120096474A1 (en) * 2010-10-15 2012-04-19 Via Technologies, Inc. Systems and Methods for Performing Multi-Program General Purpose Shader Kickoff
US8499305B2 (en) * 2010-10-15 2013-07-30 Via Technologies, Inc. Systems and methods for performing multi-program general purpose shader kickoff
US9071244B2 (en) 2012-01-26 2015-06-30 Nvidia Corporation Ground referenced single-ended signaling
US9338036B2 (en) 2012-01-30 2016-05-10 Nvidia Corporation Data-driven charge-pump transmitter for differential signaling
US9965821B2 (en) 2012-03-09 2018-05-08 Nvidia Corporation Fully parallel in-place construction of 3D acceleration structures in a graphics processing unit
US9721320B2 (en) 2012-03-09 2017-08-01 Nvidia Corporation Fully parallel in-place construction of 3D acceleration structures and bounding volume hierarchies in a graphics processing unit
US20130267835A1 (en) * 2012-04-10 2013-10-10 Jerome Ranjeev Edwards System and method for localizing medical instruments during cardiovascular medical procedures
US10433761B2 (en) 2012-04-10 2019-10-08 Cardionxt, Inc. Methods for localizing medical instruments during cardiovascular medical procedures
US9510772B2 (en) * 2012-04-10 2016-12-06 Cardionxt, Inc. System and method for localizing medical instruments during cardiovascular medical procedures
US20130342549A1 (en) * 2012-06-26 2013-12-26 Samsung Electronics Co., Ltd. Apparatus and method for processing rendering data
US9153539B2 (en) * 2013-03-15 2015-10-06 Nvidia Corporation Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US9170980B2 (en) * 2013-03-15 2015-10-27 Nvidia Corporation Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US20140281383A1 (en) * 2013-03-15 2014-09-18 Nvidia Corporation Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
TWI560819B (en) * 2013-03-15 2016-12-01 Nvidia Corp Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US9269179B2 (en) * 2013-03-15 2016-02-23 Nvidia Corporation System, method, and computer program product for generating primitive specific attributes
US9147447B2 (en) 2013-03-15 2015-09-29 Nvidia Corporation Ground-referenced single-ended memory interconnect
DE102013224636B4 (en) 2013-03-15 2024-03-14 Nvidia Corporation Ground-referenced-single-end-signaling-connected-graphics-processing-unit-multi-chip module
US9153314B2 (en) 2013-03-15 2015-10-06 Nvidia Corporation Ground-referenced single-ended memory interconnect
US20140266417A1 (en) * 2013-03-15 2014-09-18 Nvidia Corporation Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US9171607B2 (en) 2013-03-15 2015-10-27 Nvidia Corporation Ground-referenced single-ended system-on-package
CN104050618A (en) * 2013-03-15 2014-09-17 辉达公司 Ground-referenced single-ended signaling connected graphics processing unit multi-chip module
US20140267276A1 (en) * 2013-03-15 2014-09-18 Nvidia Corporation System, method, and computer program product for generating primitive specific attributes
US9955893B2 (en) 2013-08-22 2018-05-01 Aftx, Inc. Methods, systems, and apparatus for identification and characterization of rotors associated with atrial fibrillation
US9498143B2 (en) 2013-08-22 2016-11-22 Aftx, Inc. Methods, systems, and apparatus for identification and characterization of rotors associated with atrial fibrillation
US10588532B2 (en) 2013-08-22 2020-03-17 Aftx, Inc. Methods, systems, and apparatus for identification and characterization of rotors associated with atrial fibrillation
US9703604B2 (en) 2013-12-10 2017-07-11 Arm Limited Configurable thread ordering for throughput computing devices
GB2521151A (en) * 2013-12-10 2015-06-17 Advanced Risc Mach Ltd Configurable thread ordering for a data processing apparatus
US10733012B2 (en) 2013-12-10 2020-08-04 Arm Limited Configuring thread scheduling on a multi-threaded data processing apparatus
GB2521151B (en) * 2013-12-10 2021-06-02 Advanced Risc Mach Ltd Configurable thread ordering for a data processing apparatus
US20190221154A1 (en) * 2014-09-30 2019-07-18 Microsoft Technology Licensing, Llc Displaying content on a display in power save mode
US10482564B2 (en) 2016-09-12 2019-11-19 Alibaba Group Holding Limited Method and system for improving GPU performance during data-intensive visualization operations
US11004258B2 (en) * 2016-09-22 2021-05-11 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
US10460513B2 (en) * 2016-09-22 2019-10-29 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
US20200035017A1 (en) * 2016-09-22 2020-01-30 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
US11869140B2 (en) 2016-09-22 2024-01-09 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
US20180082470A1 (en) * 2016-09-22 2018-03-22 Advanced Micro Devices, Inc. Combined world-space pipeline shader stages
EP3553750A4 (en) * 2016-12-09 2020-06-10 Sony Interactive Entertainment Inc. Image processing device, image processing method, and program
US10755468B2 (en) 2016-12-09 2020-08-25 Sony Interactive Entertainment Inc. Image processing apparatus, image processing method, and program to improve speed for calculating a color of pixels in image data
US10650566B2 (en) * 2017-02-15 2020-05-12 Microsoft Technology Licensing, Llc Multiple shader processes in graphics processing
WO2018151981A1 (en) * 2017-02-15 2018-08-23 Microsoft Technology Licensing, Llc Multiple shader processes in graphics processing
CN110291563A (en) * 2017-02-15 2019-09-27 微软技术许可有限责任公司 Multiple tinter processes in graphics process
US11132759B2 (en) 2017-04-10 2021-09-28 Intel Corporation Mutli-frame renderer
US11636567B2 (en) 2017-04-10 2023-04-25 Intel Corporation Mutli-frame renderer
US10204394B2 (en) * 2017-04-10 2019-02-12 Intel Corporation Multi-frame renderer
US10847117B1 (en) * 2019-05-13 2020-11-24 Adobe Inc. Controlling an augmented reality display with transparency control using multiple sets of video buffers
US11626058B2 (en) * 2020-09-09 2023-04-11 Samsung Display Co., Ltd. Display apparatus and method of driving the same
US20230196652A1 (en) * 2021-03-05 2023-06-22 Ideapool Technology Co., Ltd. A three-dimensional image player capable of real-time interaction
WO2022251333A3 (en) * 2021-05-28 2023-01-19 MemComputing, Inc. Memory graphics processing unit
CN114463160A (en) * 2022-01-30 2022-05-10 摩尔线程智能科技(北京)有限责任公司 Parallel processing method and device for graphics pipeline and readable storage medium
CN116263981A (en) * 2022-04-20 2023-06-16 象帝先计算技术(重庆)有限公司 Graphics processor, system, apparatus, device, and method

Also Published As

Publication number Publication date
KR20080085888A (en) 2008-09-24
DE112006003473B4 (en) 2011-07-14
US8730249B2 (en) 2014-05-20
CN101371247B (en) 2014-06-04
CN101371247A (en) 2009-02-18
GB2446546A (en) 2008-08-13
GB0810493D0 (en) 2008-07-09
JP2009520307A (en) 2009-05-21
TWI368182B (en) 2012-07-11
WO2007111743A3 (en) 2008-08-28
US20120026171A1 (en) 2012-02-02
US7830392B1 (en) 2010-11-09
JP5345226B2 (en) 2013-11-20
TW200745987A (en) 2007-12-16
KR101027621B1 (en) 2011-04-06
US7728841B1 (en) 2010-06-01
JP2012178158A (en) 2012-09-13
DE112006003473T5 (en) 2008-10-23
WO2007111743A2 (en) 2007-10-04
GB2446546B (en) 2011-05-04

Similar Documents

Publication Publication Date Title
US8730249B2 (en) Parallel array architecture for a graphics processor
US8074224B1 (en) Managing state information for a multi-threaded processor
US8077174B2 (en) Hierarchical processor array
US7634637B1 (en) Execution of parallel groups of threads with per-instruction serialization
US7522171B1 (en) On-the-fly reordering of 32-bit per component texture images in a multi-cycle data transfer
US8429656B1 (en) Thread count throttling for efficient resource utilization
US7750915B1 (en) Concurrent access of data elements stored across multiple banks in a shared memory resource
US7447873B1 (en) Multithreaded SIMD parallel processor with loading of groups of threads
US7594095B1 (en) Multithreaded SIMD parallel processor with launching of groups of threads
US7747842B1 (en) Configurable output buffer ganging for a parallel processor
US8111260B2 (en) Fast reconfiguration of graphics pipeline state
US10217183B2 (en) System, method, and computer program product for simultaneous execution of compute and graphics workloads
US8087029B1 (en) Thread-type-based load balancing in a multithreaded processor
US8108872B1 (en) Thread-type-based resource allocation in a multithreaded processor
US7366842B1 (en) Creating permanent storage on the fly within existing buffers
US20100123717A1 (en) Dynamic Scheduling in a Graphics Processor
US20090179894A1 (en) Computing system capable of parallelizing the operation of multiple graphics processing pipelines (GPPLS)
US8373717B2 (en) Utilization of symmetrical properties in rendering
US7865894B1 (en) Distributing processing tasks within a processor
CN106575430B (en) Method and apparatus for pixel hashing
US7484076B1 (en) Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)
US7404056B1 (en) Virtual copying scheme for creating multiple versions of state information
US7404059B1 (en) Parallel copying scheme for creating multiple versions of state information
US7593971B1 (en) Configurable state table for managing multiple versions of state information
US7489315B1 (en) Pixel stream assembly for raster operations

Legal Events

Date Code Title Description
AS Assignment

Owner name: NVIDIA CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DANSKIN, JOHN M.;MONTRYM, JOHN S.;LINDHOLM, JOHN ERIK;AND OTHERS;REEL/FRAME:018982/0974;SIGNING DATES FROM 20070130 TO 20070307

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION